+static int radeon_get_num_tile_pipes(struct radeon *radeon)
+{
+ struct drm_radeon_info info = {};
+ uint32_t num_tile_pipes = 0;
+ int r;
+
+ info.request = RADEON_INFO_NUM_TILE_PIPES;
+ info.value = (uintptr_t)&num_tile_pipes;
+ r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info,
+ sizeof(struct drm_radeon_info));
+ if (r)
+ return r;
+
+ radeon->num_tile_pipes = num_tile_pipes;
+ return 0;
+}
+
+static int radeon_get_backend_map(struct radeon *radeon)
+{
+ struct drm_radeon_info info = {};
+ uint32_t backend_map = 0;
+ int r;
+
+ info.request = RADEON_INFO_BACKEND_MAP;
+ info.value = (uintptr_t)&backend_map;
+ r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info,
+ sizeof(struct drm_radeon_info));
+ if (r)
+ return r;
+
+ radeon->backend_map = backend_map;
+ radeon->backend_map_valid = TRUE;
+
+ return 0;
+}
+