+ /* Special case: on pre-Gen7 hardware that supports PLN, the second operand
+ * of a PLN instruction needs to be an even-numbered register, so we have a
+ * special register class aligned_bary_class to handle this case.
+ */
+ if (compiler->fs_reg_sets[rsi].aligned_bary_class >= 0) {
+ foreach_block_and_inst(block, fs_inst, inst, fs->cfg) {
+ if (inst->opcode == FS_OPCODE_LINTERP && inst->src[0].file == VGRF &&
+ fs->alloc.sizes[inst->src[0].nr] ==
+ aligned_bary_size(fs->dispatch_width)) {
+ ra_set_node_class(g, first_vgrf_node + inst->src[0].nr,
+ compiler->fs_reg_sets[rsi].aligned_bary_class);
+ }
+ }
+ }
+
+ /* Add interference based on the live range of the register */
+ for (unsigned i = 0; i < fs->alloc.count; i++) {