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pan/bi: Flesh out st_vary IR
[mesa.git]
/
src
/
intel
/
compiler
/
brw_shader.cpp
diff --git
a/src/intel/compiler/brw_shader.cpp
b/src/intel/compiler/brw_shader.cpp
index f95fcd99e67ac43435cfdf919ad49041b927421c..72478e3c39e6539b830226879ede817b28aff962 100644
(file)
--- a/
src/intel/compiler/brw_shader.cpp
+++ b/
src/intel/compiler/brw_shader.cpp
@@
-323,6
+323,8
@@
brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
return "typed_surface_write_logical";
case SHADER_OPCODE_MEMORY_FENCE:
return "memory_fence";
return "typed_surface_write_logical";
case SHADER_OPCODE_MEMORY_FENCE:
return "memory_fence";
+ case FS_OPCODE_SCHEDULING_FENCE:
+ return "scheduling_fence";
case SHADER_OPCODE_INTERLOCK:
/* For an interlock we actually issue a memory fence via sendc. */
return "interlock";
case SHADER_OPCODE_INTERLOCK:
/* For an interlock we actually issue a memory fence via sendc. */
return "interlock";
@@
-362,6
+364,9
@@
brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
case SHADER_OPCODE_FIND_LIVE_CHANNEL:
return "find_live_channel";
case SHADER_OPCODE_FIND_LIVE_CHANNEL:
return "find_live_channel";
+ case FS_OPCODE_LOAD_LIVE_CHANNELS:
+ return "load_live_channels";
+
case SHADER_OPCODE_BROADCAST:
return "broadcast";
case SHADER_OPCODE_SHUFFLE:
case SHADER_OPCODE_BROADCAST:
return "broadcast";
case SHADER_OPCODE_SHUFFLE:
@@
-491,6
+496,10
@@
brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
return "barrier";
case SHADER_OPCODE_MULH:
return "mulh";
return "barrier";
case SHADER_OPCODE_MULH:
return "mulh";
+ case SHADER_OPCODE_ISUB_SAT:
+ return "isub_sat";
+ case SHADER_OPCODE_USUB_SAT:
+ return "usub_sat";
case SHADER_OPCODE_MOV_INDIRECT:
return "mov_indirect";
case SHADER_OPCODE_MOV_INDIRECT:
return "mov_indirect";
@@
-694,7
+703,7
@@
backend_shader::backend_shader(const struct brw_compiler *compiler,
nir(shader),
stage_prog_data(stage_prog_data),
mem_ctx(mem_ctx),
nir(shader),
stage_prog_data(stage_prog_data),
mem_ctx(mem_ctx),
- cfg(NULL),
+ cfg(NULL),
idom_analysis(this),
stage(shader->info.stage)
{
debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
stage(shader->info.stage)
{
debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
@@
-1076,6
+1085,7
@@
backend_instruction::has_side_effects() const
case TCS_OPCODE_RELEASE_INPUT:
case SHADER_OPCODE_RND_MODE:
case SHADER_OPCODE_FLOAT_CONTROL_MODE:
case TCS_OPCODE_RELEASE_INPUT:
case SHADER_OPCODE_RND_MODE:
case SHADER_OPCODE_FLOAT_CONTROL_MODE:
+ case FS_OPCODE_SCHEDULING_FENCE:
return true;
default:
return eot;
return true;
default:
return eot;
@@
-1191,13
+1201,13
@@
backend_instruction::remove(bblock_t *block)
}
void
}
void
-backend_shader::dump_instructions()
+backend_shader::dump_instructions()
const
{
dump_instructions(NULL);
}
void
{
dump_instructions(NULL);
}
void
-backend_shader::dump_instructions(const char *name)
+backend_shader::dump_instructions(const char *name)
const
{
FILE *file = stderr;
if (name && geteuid() != 0) {
{
FILE *file = stderr;
if (name && geteuid() != 0) {
@@
-1232,7
+1242,13
@@
backend_shader::calculate_cfg()
{
if (this->cfg)
return;
{
if (this->cfg)
return;
- cfg = new(mem_ctx) cfg_t(&this->instructions);
+ cfg = new(mem_ctx) cfg_t(this, &this->instructions);
+}
+
+void
+backend_shader::invalidate_analysis(brw::analysis_dependency_class c)
+{
+ idom_analysis.invalidate(c);
}
extern "C" const unsigned *
}
extern "C" const unsigned *
@@
-1345,8
+1361,7
@@
brw_compile_tes(const struct brw_compiler *compiler,
prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
fs_generator g(compiler, log_data, mem_ctx,
prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
fs_generator g(compiler, log_data, mem_ctx,
- &prog_data->base.base, v.shader_stats, false,
- MESA_SHADER_TESS_EVAL);
+ &prog_data->base.base, false, MESA_SHADER_TESS_EVAL);
if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
g.enable_debug(ralloc_asprintf(mem_ctx,
"%s tessellation evaluation shader %s",
if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
g.enable_debug(ralloc_asprintf(mem_ctx,
"%s tessellation evaluation shader %s",
@@
-1355,7
+1370,7
@@
brw_compile_tes(const struct brw_compiler *compiler,
nir->info.name));
}
nir->info.name));
}
- g.generate_code(v.cfg, 8, stats);
+ g.generate_code(v.cfg, 8,
v.shader_stats,
stats);
assembly = g.get_assembly();
} else {
assembly = g.get_assembly();
} else {