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intel/compiler: use the same name for nir shaders in brw_compile_* functions
[mesa.git]
/
src
/
intel
/
compiler
/
brw_vec4.cpp
diff --git
a/src/intel/compiler/brw_vec4.cpp
b/src/intel/compiler/brw_vec4.cpp
index 5f7decd5410f7990118407ce8bd0e495fb40851a..ee91be0a7ab6469ff4a12c8b83209d4cf70630af 100644
(file)
--- a/
src/intel/compiler/brw_vec4.cpp
+++ b/
src/intel/compiler/brw_vec4.cpp
@@
-26,7
+26,6
@@
#include "brw_cfg.h"
#include "brw_nir.h"
#include "brw_vec4_builder.h"
#include "brw_cfg.h"
#include "brw_nir.h"
#include "brw_vec4_builder.h"
-#include "brw_vec4_live_variables.h"
#include "brw_vec4_vs.h"
#include "brw_dead_control_flow.h"
#include "dev/gen_debug.h"
#include "brw_vec4_vs.h"
#include "brw_dead_control_flow.h"
#include "dev/gen_debug.h"
@@
-148,7
+147,7
@@
dst_reg::equals(const dst_reg &r) const
}
bool
}
bool
-vec4_instruction::is_send_from_grf()
+vec4_instruction::is_send_from_grf()
const
{
switch (opcode) {
case SHADER_OPCODE_SHADER_TIME_ADD:
{
switch (opcode) {
case SHADER_OPCODE_SHADER_TIME_ADD:
@@
-327,13
+326,13
@@
vec4_instruction::can_change_types() const
* instruction -- the generate_* functions generate additional MOVs
* for setup.
*/
* instruction -- the generate_* functions generate additional MOVs
* for setup.
*/
-int
-vec4_
visitor::implied_mrf_writes(vec4_instruction *inst)
+unsigned
+vec4_
instruction::implied_mrf_writes() const
{
{
- if (
inst->mlen == 0 || inst->
is_send_from_grf())
+ if (
mlen == 0 ||
is_send_from_grf())
return 0;
return 0;
- switch (
inst->
opcode) {
+ switch (opcode) {
case SHADER_OPCODE_RCP:
case SHADER_OPCODE_RSQ:
case SHADER_OPCODE_SQRT:
case SHADER_OPCODE_RCP:
case SHADER_OPCODE_RSQ:
case SHADER_OPCODE_SQRT:
@@
-377,7
+376,7
@@
vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
case SHADER_OPCODE_TG4_OFFSET:
case SHADER_OPCODE_SAMPLEINFO:
case SHADER_OPCODE_GET_BUFFER_SIZE:
case SHADER_OPCODE_TG4_OFFSET:
case SHADER_OPCODE_SAMPLEINFO:
case SHADER_OPCODE_GET_BUFFER_SIZE:
- return
inst->
header_size;
+ return header_size;
default:
unreachable("not reached");
}
default:
unreachable("not reached");
}
@@
-497,7
+496,7
@@
vec4_visitor::opt_vector_float()
}
if (progress)
}
if (progress)
- invalidate_
live_intervals(
);
+ invalidate_
analysis(DEPENDENCY_INSTRUCTIONS
);
return progress;
}
return progress;
}
@@
-578,7
+577,7
@@
vec4_visitor::opt_reduce_swizzle()
}
if (progress)
}
if (progress)
- invalidate_
live_intervals(
);
+ invalidate_
analysis(DEPENDENCY_INSTRUCTION_DETAIL
);
return progress;
}
return progress;
}
@@
-633,6
+632,9
@@
set_push_constant_loc(const int nr_uniforms, int *new_uniform_count,
void
vec4_visitor::pack_uniform_registers()
{
void
vec4_visitor::pack_uniform_registers()
{
+ if (!compiler->compact_params)
+ return;
+
uint8_t chans_used[this->uniforms];
int new_loc[this->uniforms];
int new_chan[this->uniforms];
uint8_t chans_used[this->uniforms];
int new_loc[this->uniforms];
int new_chan[this->uniforms];
@@
-902,7
+904,8
@@
vec4_visitor::opt_algebraic()
}
if (progress)
}
if (progress)
- invalidate_live_intervals();
+ invalidate_analysis(DEPENDENCY_INSTRUCTION_DATA_FLOW |
+ DEPENDENCY_INSTRUCTION_DETAIL);
return progress;
}
return progress;
}
@@
-1250,8
+1253,7
@@
vec4_visitor::opt_register_coalesce()
{
bool progress = false;
int next_ip = 0;
{
bool progress = false;
int next_ip = 0;
-
- calculate_live_intervals();
+ const vec4_live_variables &live = live_analysis.require();
foreach_block_and_inst_safe (block, vec4_instruction, inst, cfg) {
int ip = next_ip;
foreach_block_and_inst_safe (block, vec4_instruction, inst, cfg) {
int ip = next_ip;
@@
-1293,7
+1295,7
@@
vec4_visitor::opt_register_coalesce()
/* Can't coalesce this GRF if someone else was going to
* read it later.
*/
/* Can't coalesce this GRF if someone else was going to
* read it later.
*/
- if (var_range_end(var_from_reg(alloc, dst_reg(inst->src[0])), 8) > ip)
+ if (
live.
var_range_end(var_from_reg(alloc, dst_reg(inst->src[0])), 8) > ip)
continue;
/* We need to check interference with the final destination between this
continue;
/* We need to check interference with the final destination between this
@@
-1472,7
+1474,7
@@
vec4_visitor::opt_register_coalesce()
}
if (progress)
}
if (progress)
- invalidate_
live_intervals(
);
+ invalidate_
analysis(DEPENDENCY_INSTRUCTIONS
);
return progress;
}
return progress;
}
@@
-1522,6
+1524,9
@@
vec4_visitor::eliminate_find_live_channel()
}
}
}
}
+ if (progress)
+ invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL);
+
return progress;
}
return progress;
}
@@
-1596,19
+1601,19
@@
vec4_visitor::split_virtual_grfs()
}
}
}
}
}
}
- invalidate_
live_intervals(
);
+ invalidate_
analysis(DEPENDENCY_INSTRUCTION_DETAIL | DEPENDENCY_VARIABLES
);
}
void
}
void
-vec4_visitor::dump_instruction(
backend_instruction *be_inst)
+vec4_visitor::dump_instruction(
const backend_instruction *be_inst) const
{
dump_instruction(be_inst, stderr);
}
void
{
dump_instruction(be_inst, stderr);
}
void
-vec4_visitor::dump_instruction(
backend_instruction *be_inst, FILE *file)
+vec4_visitor::dump_instruction(
const backend_instruction *be_inst, FILE *file) const
{
{
-
vec4_instruction *inst = (
vec4_instruction *)be_inst;
+
const vec4_instruction *inst = (const
vec4_instruction *)be_inst;
if (inst->predicate) {
fprintf(file, "(%cf%d.%d%s) ",
if (inst->predicate) {
fprintf(file, "(%cf%d.%d%s) ",
@@
-1899,7
+1904,7
@@
vec4_visitor::lower_minmax()
}
if (progress)
}
if (progress)
- invalidate_
live_intervals(
);
+ invalidate_
analysis(DEPENDENCY_INSTRUCTIONS
);
return progress;
}
return progress;
}
@@
-2035,7
+2040,8
@@
vec4_visitor::fixup_3src_null_dest()
}
if (progress)
}
if (progress)
- invalidate_live_intervals();
+ invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL |
+ DEPENDENCY_VARIABLES);
}
void
}
void
@@
-2363,7
+2369,7
@@
vec4_visitor::lower_simd_width()
}
if (progress)
}
if (progress)
- invalidate_
live_intervals(
);
+ invalidate_
analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES
);
return progress;
}
return progress;
}
@@
-2520,7
+2526,7
@@
vec4_visitor::scalarize_df()
}
if (progress)
}
if (progress)
- invalidate_
live_intervals(
);
+ invalidate_
analysis(DEPENDENCY_INSTRUCTIONS
);
return progress;
}
return progress;
}
@@
-2563,7
+2569,7
@@
vec4_visitor::lower_64bit_mad_to_mul_add()
}
if (progress)
}
if (progress)
- invalidate_
live_intervals(
);
+ invalidate_
analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES
);
return progress;
}
return progress;
}
@@
-2660,6
+2666,13
@@
vec4_visitor::apply_logical_swizzle(struct brw_reg *hw_reg,
}
}
}
}
+void
+vec4_visitor::invalidate_analysis(brw::analysis_dependency_class c)
+{
+ backend_shader::invalidate_analysis(c);
+ live_analysis.invalidate(c);
+}
+
bool
vec4_visitor::run()
{
bool
vec4_visitor::run()
{
@@
-2840,12
+2853,13
@@
brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
const struct brw_vs_prog_key *key,
struct brw_vs_prog_data *prog_data,
void *mem_ctx,
const struct brw_vs_prog_key *key,
struct brw_vs_prog_data *prog_data,
- nir_shader *
shade
r,
+ nir_shader *
ni
r,
int shader_time_index,
int shader_time_index,
+ struct brw_compile_stats *stats,
char **error_str)
{
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_VERTEX];
char **error_str)
{
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_VERTEX];
- brw_nir_apply_key(
shader, compiler, &key->base
, is_scalar);
+ brw_nir_apply_key(
nir, compiler, &key->base, 8
, is_scalar);
const unsigned *assembly = NULL;
const unsigned *assembly = NULL;
@@
-2861,28
+2875,28
@@
brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
*/
assert(!is_scalar);
assert(key->copy_edgeflag);
*/
assert(!is_scalar);
assert(key->copy_edgeflag);
-
shade
r->info.inputs_read |= VERT_BIT_EDGEFLAG;
+
ni
r->info.inputs_read |= VERT_BIT_EDGEFLAG;
}
}
- prog_data->inputs_read =
shade
r->info.inputs_read;
- prog_data->double_inputs_read =
shade
r->info.vs.double_inputs;
+ prog_data->inputs_read =
ni
r->info.inputs_read;
+ prog_data->double_inputs_read =
ni
r->info.vs.double_inputs;
- brw_nir_lower_vs_inputs(
shade
r, key->gl_attrib_wa_flags);
- brw_nir_lower_vue_outputs(
shade
r);
- brw_postprocess_nir(
shade
r, compiler, is_scalar);
+ brw_nir_lower_vs_inputs(
ni
r, key->gl_attrib_wa_flags);
+ brw_nir_lower_vue_outputs(
ni
r);
+ brw_postprocess_nir(
ni
r, compiler, is_scalar);
prog_data->base.clip_distance_mask =
prog_data->base.clip_distance_mask =
- ((1 <<
shade
r->info.clip_distance_array_size) - 1);
+ ((1 <<
ni
r->info.clip_distance_array_size) - 1);
prog_data->base.cull_distance_mask =
prog_data->base.cull_distance_mask =
- ((1 <<
shade
r->info.cull_distance_array_size) - 1) <<
-
shade
r->info.clip_distance_array_size;
+ ((1 <<
ni
r->info.cull_distance_array_size) - 1) <<
+
ni
r->info.clip_distance_array_size;
unsigned nr_attribute_slots = util_bitcount64(prog_data->inputs_read);
/* gl_VertexID and gl_InstanceID are system values, but arrive via an
* incoming vertex attribute. So, add an extra slot.
*/
unsigned nr_attribute_slots = util_bitcount64(prog_data->inputs_read);
/* gl_VertexID and gl_InstanceID are system values, but arrive via an
* incoming vertex attribute. So, add an extra slot.
*/
- if (
shade
r->info.system_values_read &
+ if (
ni
r->info.system_values_read &
(BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) |
BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) |
(BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) |
BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) |
@@
-2891,33
+2905,33
@@
brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
}
/* gl_DrawID and IsIndexedDraw share its very own vec4 */
}
/* gl_DrawID and IsIndexedDraw share its very own vec4 */
- if (
shade
r->info.system_values_read &
+ if (
ni
r->info.system_values_read &
(BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID) |
BITFIELD64_BIT(SYSTEM_VALUE_IS_INDEXED_DRAW))) {
nr_attribute_slots++;
}
(BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID) |
BITFIELD64_BIT(SYSTEM_VALUE_IS_INDEXED_DRAW))) {
nr_attribute_slots++;
}
- if (
shade
r->info.system_values_read &
+ if (
ni
r->info.system_values_read &
BITFIELD64_BIT(SYSTEM_VALUE_IS_INDEXED_DRAW))
prog_data->uses_is_indexed_draw = true;
BITFIELD64_BIT(SYSTEM_VALUE_IS_INDEXED_DRAW))
prog_data->uses_is_indexed_draw = true;
- if (
shade
r->info.system_values_read &
+ if (
ni
r->info.system_values_read &
BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX))
prog_data->uses_firstvertex = true;
BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX))
prog_data->uses_firstvertex = true;
- if (
shade
r->info.system_values_read &
+ if (
ni
r->info.system_values_read &
BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE))
prog_data->uses_baseinstance = true;
BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE))
prog_data->uses_baseinstance = true;
- if (
shade
r->info.system_values_read &
+ if (
ni
r->info.system_values_read &
BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE))
prog_data->uses_vertexid = true;
BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE))
prog_data->uses_vertexid = true;
- if (
shade
r->info.system_values_read &
+ if (
ni
r->info.system_values_read &
BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID))
prog_data->uses_instanceid = true;
BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID))
prog_data->uses_instanceid = true;
- if (
shade
r->info.system_values_read &
+ if (
ni
r->info.system_values_read &
BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID))
prog_data->uses_drawid = true;
BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID))
prog_data->uses_drawid = true;
@@
-2963,8
+2977,7
@@
brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
fs_visitor v(compiler, log_data, mem_ctx, &key->base,
&prog_data->base.base,
fs_visitor v(compiler, log_data, mem_ctx, &key->base,
&prog_data->base.base,
- NULL, /* prog; Only used for TEXTURE_RECTANGLE on gen < 8 */
- shader, 8, shader_time_index);
+ nir, 8, shader_time_index);
if (!v.run_vs()) {
if (error_str)
*error_str = ralloc_strdup(mem_ctx, v.fail_msg);
if (!v.run_vs()) {
if (error_str)
*error_str = ralloc_strdup(mem_ctx, v.fail_msg);
@@
-2975,18
+2988,20
@@
brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
fs_generator g(compiler, log_data, mem_ctx,
prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
fs_generator g(compiler, log_data, mem_ctx,
- &prog_data->base.base, v.
promoted_constants
,
-
v.runtime_check_aads_emit,
MESA_SHADER_VERTEX);
+ &prog_data->base.base, v.
runtime_check_aads_emit
,
+ MESA_SHADER_VERTEX);
if (INTEL_DEBUG & DEBUG_VS) {
const char *debug_name =
ralloc_asprintf(mem_ctx, "%s vertex shader %s",
if (INTEL_DEBUG & DEBUG_VS) {
const char *debug_name =
ralloc_asprintf(mem_ctx, "%s vertex shader %s",
-
shader->info.label ? shade
r->info.label :
+
nir->info.label ? ni
r->info.label :
"unnamed",
"unnamed",
-
shade
r->info.name);
+
ni
r->info.name);
g.enable_debug(debug_name);
}
g.enable_debug(debug_name);
}
- g.generate_code(v.cfg, 8);
+ g.generate_code(v.cfg, 8, v.shader_stats,
+ v.performance_analysis.require(), stats);
+ g.add_const_data(nir->constant_data, nir->constant_data_size);
assembly = g.get_assembly();
}
assembly = g.get_assembly();
}
@@
-2994,7
+3009,7
@@
brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
vec4_vs_visitor v(compiler, log_data, key, prog_data,
prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
vec4_vs_visitor v(compiler, log_data, key, prog_data,
-
shade
r, mem_ctx, shader_time_index);
+
ni
r, mem_ctx, shader_time_index);
if (!v.run()) {
if (error_str)
*error_str = ralloc_strdup(mem_ctx, v.fail_msg);
if (!v.run()) {
if (error_str)
*error_str = ralloc_strdup(mem_ctx, v.fail_msg);
@@
-3003,7
+3018,10
@@
brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
}
assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx,
}
assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx,
- shader, &prog_data->base, v.cfg);
+ nir, &prog_data->base,
+ v.cfg,
+ v.performance_analysis.require(),
+ stats);
}
return assembly;
}
return assembly;