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intel/compiler: use the same name for nir shaders in brw_compile_* functions
[mesa.git]
/
src
/
intel
/
compiler
/
brw_vec4.cpp
diff --git
a/src/intel/compiler/brw_vec4.cpp
b/src/intel/compiler/brw_vec4.cpp
index 864ece7e636fb8221b2111b59a5777e306d87e80..ee91be0a7ab6469ff4a12c8b83209d4cf70630af 100644
(file)
--- a/
src/intel/compiler/brw_vec4.cpp
+++ b/
src/intel/compiler/brw_vec4.cpp
@@
-2853,13
+2853,13
@@
brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
const struct brw_vs_prog_key *key,
struct brw_vs_prog_data *prog_data,
void *mem_ctx,
const struct brw_vs_prog_key *key,
struct brw_vs_prog_data *prog_data,
- nir_shader *
shade
r,
+ nir_shader *
ni
r,
int shader_time_index,
struct brw_compile_stats *stats,
char **error_str)
{
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_VERTEX];
int shader_time_index,
struct brw_compile_stats *stats,
char **error_str)
{
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_VERTEX];
- brw_nir_apply_key(
shade
r, compiler, &key->base, 8, is_scalar);
+ brw_nir_apply_key(
ni
r, compiler, &key->base, 8, is_scalar);
const unsigned *assembly = NULL;
const unsigned *assembly = NULL;
@@
-2875,28
+2875,28
@@
brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
*/
assert(!is_scalar);
assert(key->copy_edgeflag);
*/
assert(!is_scalar);
assert(key->copy_edgeflag);
-
shade
r->info.inputs_read |= VERT_BIT_EDGEFLAG;
+
ni
r->info.inputs_read |= VERT_BIT_EDGEFLAG;
}
}
- prog_data->inputs_read =
shade
r->info.inputs_read;
- prog_data->double_inputs_read =
shade
r->info.vs.double_inputs;
+ prog_data->inputs_read =
ni
r->info.inputs_read;
+ prog_data->double_inputs_read =
ni
r->info.vs.double_inputs;
- brw_nir_lower_vs_inputs(
shade
r, key->gl_attrib_wa_flags);
- brw_nir_lower_vue_outputs(
shade
r);
- brw_postprocess_nir(
shade
r, compiler, is_scalar);
+ brw_nir_lower_vs_inputs(
ni
r, key->gl_attrib_wa_flags);
+ brw_nir_lower_vue_outputs(
ni
r);
+ brw_postprocess_nir(
ni
r, compiler, is_scalar);
prog_data->base.clip_distance_mask =
prog_data->base.clip_distance_mask =
- ((1 <<
shade
r->info.clip_distance_array_size) - 1);
+ ((1 <<
ni
r->info.clip_distance_array_size) - 1);
prog_data->base.cull_distance_mask =
prog_data->base.cull_distance_mask =
- ((1 <<
shade
r->info.cull_distance_array_size) - 1) <<
-
shade
r->info.clip_distance_array_size;
+ ((1 <<
ni
r->info.cull_distance_array_size) - 1) <<
+
ni
r->info.clip_distance_array_size;
unsigned nr_attribute_slots = util_bitcount64(prog_data->inputs_read);
/* gl_VertexID and gl_InstanceID are system values, but arrive via an
* incoming vertex attribute. So, add an extra slot.
*/
unsigned nr_attribute_slots = util_bitcount64(prog_data->inputs_read);
/* gl_VertexID and gl_InstanceID are system values, but arrive via an
* incoming vertex attribute. So, add an extra slot.
*/
- if (
shade
r->info.system_values_read &
+ if (
ni
r->info.system_values_read &
(BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) |
BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) |
(BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) |
BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) |
@@
-2905,33
+2905,33
@@
brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
}
/* gl_DrawID and IsIndexedDraw share its very own vec4 */
}
/* gl_DrawID and IsIndexedDraw share its very own vec4 */
- if (
shade
r->info.system_values_read &
+ if (
ni
r->info.system_values_read &
(BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID) |
BITFIELD64_BIT(SYSTEM_VALUE_IS_INDEXED_DRAW))) {
nr_attribute_slots++;
}
(BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID) |
BITFIELD64_BIT(SYSTEM_VALUE_IS_INDEXED_DRAW))) {
nr_attribute_slots++;
}
- if (
shade
r->info.system_values_read &
+ if (
ni
r->info.system_values_read &
BITFIELD64_BIT(SYSTEM_VALUE_IS_INDEXED_DRAW))
prog_data->uses_is_indexed_draw = true;
BITFIELD64_BIT(SYSTEM_VALUE_IS_INDEXED_DRAW))
prog_data->uses_is_indexed_draw = true;
- if (
shade
r->info.system_values_read &
+ if (
ni
r->info.system_values_read &
BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX))
prog_data->uses_firstvertex = true;
BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX))
prog_data->uses_firstvertex = true;
- if (
shade
r->info.system_values_read &
+ if (
ni
r->info.system_values_read &
BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE))
prog_data->uses_baseinstance = true;
BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE))
prog_data->uses_baseinstance = true;
- if (
shade
r->info.system_values_read &
+ if (
ni
r->info.system_values_read &
BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE))
prog_data->uses_vertexid = true;
BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE))
prog_data->uses_vertexid = true;
- if (
shade
r->info.system_values_read &
+ if (
ni
r->info.system_values_read &
BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID))
prog_data->uses_instanceid = true;
BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID))
prog_data->uses_instanceid = true;
- if (
shade
r->info.system_values_read &
+ if (
ni
r->info.system_values_read &
BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID))
prog_data->uses_drawid = true;
BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID))
prog_data->uses_drawid = true;
@@
-2977,7
+2977,7
@@
brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
fs_visitor v(compiler, log_data, mem_ctx, &key->base,
&prog_data->base.base,
fs_visitor v(compiler, log_data, mem_ctx, &key->base,
&prog_data->base.base,
-
shade
r, 8, shader_time_index);
+
ni
r, 8, shader_time_index);
if (!v.run_vs()) {
if (error_str)
*error_str = ralloc_strdup(mem_ctx, v.fail_msg);
if (!v.run_vs()) {
if (error_str)
*error_str = ralloc_strdup(mem_ctx, v.fail_msg);
@@
-2993,14
+2993,15
@@
brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
if (INTEL_DEBUG & DEBUG_VS) {
const char *debug_name =
ralloc_asprintf(mem_ctx, "%s vertex shader %s",
if (INTEL_DEBUG & DEBUG_VS) {
const char *debug_name =
ralloc_asprintf(mem_ctx, "%s vertex shader %s",
-
shader->info.label ? shade
r->info.label :
+
nir->info.label ? ni
r->info.label :
"unnamed",
"unnamed",
-
shade
r->info.name);
+
ni
r->info.name);
g.enable_debug(debug_name);
}
g.generate_code(v.cfg, 8, v.shader_stats,
v.performance_analysis.require(), stats);
g.enable_debug(debug_name);
}
g.generate_code(v.cfg, 8, v.shader_stats,
v.performance_analysis.require(), stats);
+ g.add_const_data(nir->constant_data, nir->constant_data_size);
assembly = g.get_assembly();
}
assembly = g.get_assembly();
}
@@
-3008,7
+3009,7
@@
brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
vec4_vs_visitor v(compiler, log_data, key, prog_data,
prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
vec4_vs_visitor v(compiler, log_data, key, prog_data,
-
shade
r, mem_ctx, shader_time_index);
+
ni
r, mem_ctx, shader_time_index);
if (!v.run()) {
if (error_str)
*error_str = ralloc_strdup(mem_ctx, v.fail_msg);
if (!v.run()) {
if (error_str)
*error_str = ralloc_strdup(mem_ctx, v.fail_msg);
@@
-3017,7
+3018,7
@@
brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
}
assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx,
}
assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx,
-
shade
r, &prog_data->base,
+
ni
r, &prog_data->base,
v.cfg,
v.performance_analysis.require(),
stats);
v.cfg,
v.performance_analysis.require(),
stats);