+VkResult
+anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
+ uint32_t num_entries,
+ uint32_t *state_offset,
+ struct anv_state *bt_state)
+{
+ *bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
+ state_offset);
+ if (bt_state->map == NULL) {
+ /* We ran out of space. Grab a new binding table block. */
+ VkResult result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
+ if (result != VK_SUCCESS)
+ return result;
+
+ /* Re-emit state base addresses so we get the new surface state base
+ * address before we start emitting binding tables etc.
+ */
+ anv_cmd_buffer_emit_state_base_address(cmd_buffer);
+
+ *bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
+ state_offset);
+ assert(bt_state->map != NULL);
+ }
+
+ return VK_SUCCESS;
+}
+
+static VkResult
+binding_table_for_surface_state(struct anv_cmd_buffer *cmd_buffer,
+ struct anv_state surface_state,
+ uint32_t *bt_offset)
+{
+ uint32_t state_offset;
+ struct anv_state bt_state;
+
+ VkResult result =
+ anv_cmd_buffer_alloc_blorp_binding_table(cmd_buffer, 1, &state_offset,
+ &bt_state);
+ if (result != VK_SUCCESS)
+ return result;
+
+ uint32_t *bt_map = bt_state.map;
+ bt_map[0] = surface_state.offset + state_offset;
+
+ *bt_offset = bt_state.offset;
+ return VK_SUCCESS;
+}
+
+static void
+clear_color_attachment(struct anv_cmd_buffer *cmd_buffer,
+ struct blorp_batch *batch,
+ const VkClearAttachment *attachment,
+ uint32_t rectCount, const VkClearRect *pRects)
+{
+ const struct anv_subpass *subpass = cmd_buffer->state.subpass;
+ const uint32_t color_att = attachment->colorAttachment;
+ const uint32_t att_idx = subpass->color_attachments[color_att].attachment;
+
+ if (att_idx == VK_ATTACHMENT_UNUSED)
+ return;
+
+ struct anv_render_pass_attachment *pass_att =
+ &cmd_buffer->state.pass->attachments[att_idx];
+ struct anv_attachment_state *att_state =
+ &cmd_buffer->state.attachments[att_idx];
+
+ uint32_t binding_table;
+ VkResult result =
+ binding_table_for_surface_state(cmd_buffer, att_state->color_rt_state,
+ &binding_table);
+ if (result != VK_SUCCESS)
+ return;
+
+ union isl_color_value clear_color =
+ vk_to_isl_color(attachment->clearValue.color);
+
+ /* If multiview is enabled we ignore baseArrayLayer and layerCount */
+ if (subpass->view_mask) {
+ uint32_t view_idx;
+ for_each_bit(view_idx, subpass->view_mask) {
+ for (uint32_t r = 0; r < rectCount; ++r) {
+ const VkOffset2D offset = pRects[r].rect.offset;
+ const VkExtent2D extent = pRects[r].rect.extent;
+ blorp_clear_attachments(batch, binding_table,
+ ISL_FORMAT_UNSUPPORTED, pass_att->samples,
+ view_idx, 1,
+ offset.x, offset.y,
+ offset.x + extent.width,
+ offset.y + extent.height,
+ true, clear_color, false, 0.0f, 0, 0);
+ }
+ }
+ return;
+ }
+
+ for (uint32_t r = 0; r < rectCount; ++r) {
+ const VkOffset2D offset = pRects[r].rect.offset;
+ const VkExtent2D extent = pRects[r].rect.extent;
+ blorp_clear_attachments(batch, binding_table,
+ ISL_FORMAT_UNSUPPORTED, pass_att->samples,
+ pRects[r].baseArrayLayer,
+ pRects[r].layerCount,
+ offset.x, offset.y,
+ offset.x + extent.width, offset.y + extent.height,
+ true, clear_color, false, 0.0f, 0, 0);
+ }
+}
+
+static void
+clear_depth_stencil_attachment(struct anv_cmd_buffer *cmd_buffer,
+ struct blorp_batch *batch,
+ const VkClearAttachment *attachment,
+ uint32_t rectCount, const VkClearRect *pRects)
+{
+ static const union isl_color_value color_value = { .u32 = { 0, } };
+ const struct anv_subpass *subpass = cmd_buffer->state.subpass;
+ const uint32_t att_idx = subpass->depth_stencil_attachment.attachment;
+
+ if (att_idx == VK_ATTACHMENT_UNUSED)
+ return;
+
+ struct anv_render_pass_attachment *pass_att =
+ &cmd_buffer->state.pass->attachments[att_idx];
+
+ bool clear_depth = attachment->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT;
+ bool clear_stencil = attachment->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT;
+
+ enum isl_format depth_format = ISL_FORMAT_UNSUPPORTED;
+ if (clear_depth) {
+ depth_format = anv_get_isl_format(&cmd_buffer->device->info,
+ pass_att->format,
+ VK_IMAGE_ASPECT_DEPTH_BIT,
+ VK_IMAGE_TILING_OPTIMAL);
+ }
+
+ uint32_t binding_table;
+ VkResult result =
+ binding_table_for_surface_state(cmd_buffer,
+ cmd_buffer->state.null_surface_state,
+ &binding_table);
+ if (result != VK_SUCCESS)
+ return;
+
+ /* If multiview is enabled we ignore baseArrayLayer and layerCount */
+ if (subpass->view_mask) {
+ uint32_t view_idx;
+ for_each_bit(view_idx, subpass->view_mask) {
+ for (uint32_t r = 0; r < rectCount; ++r) {
+ const VkOffset2D offset = pRects[r].rect.offset;
+ const VkExtent2D extent = pRects[r].rect.extent;
+ VkClearDepthStencilValue value = attachment->clearValue.depthStencil;
+ blorp_clear_attachments(batch, binding_table,
+ depth_format, pass_att->samples,
+ view_idx, 1,
+ offset.x, offset.y,
+ offset.x + extent.width,
+ offset.y + extent.height,
+ false, color_value,
+ clear_depth, value.depth,
+ clear_stencil ? 0xff : 0, value.stencil);
+ }
+ }
+ return;
+ }
+
+ for (uint32_t r = 0; r < rectCount; ++r) {
+ const VkOffset2D offset = pRects[r].rect.offset;
+ const VkExtent2D extent = pRects[r].rect.extent;
+ VkClearDepthStencilValue value = attachment->clearValue.depthStencil;
+ blorp_clear_attachments(batch, binding_table,
+ depth_format, pass_att->samples,
+ pRects[r].baseArrayLayer,
+ pRects[r].layerCount,
+ offset.x, offset.y,
+ offset.x + extent.width, offset.y + extent.height,
+ false, color_value,
+ clear_depth, value.depth,
+ clear_stencil ? 0xff : 0, value.stencil);
+ }
+}
+
+void anv_CmdClearAttachments(
+ VkCommandBuffer commandBuffer,
+ uint32_t attachmentCount,
+ const VkClearAttachment* pAttachments,
+ uint32_t rectCount,
+ const VkClearRect* pRects)
+{
+ ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
+
+ /* Because this gets called within a render pass, we tell blorp not to
+ * trash our depth and stencil buffers.
+ */
+ struct blorp_batch batch;
+ blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer,
+ BLORP_BATCH_NO_EMIT_DEPTH_STENCIL);
+
+ for (uint32_t a = 0; a < attachmentCount; ++a) {
+ if (pAttachments[a].aspectMask == VK_IMAGE_ASPECT_COLOR_BIT) {
+ clear_color_attachment(cmd_buffer, &batch,
+ &pAttachments[a],
+ rectCount, pRects);
+ } else {
+ clear_depth_stencil_attachment(cmd_buffer, &batch,
+ &pAttachments[a],
+ rectCount, pRects);
+ }
+ }
+
+ blorp_batch_finish(&batch);
+}
+
+enum subpass_stage {
+ SUBPASS_STAGE_LOAD,
+ SUBPASS_STAGE_DRAW,
+ SUBPASS_STAGE_RESOLVE,
+};
+
+static bool
+subpass_needs_clear(const struct anv_cmd_buffer *cmd_buffer)
+{
+ const struct anv_cmd_state *cmd_state = &cmd_buffer->state;
+ uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
+
+ for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
+ uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
+ if (a == VK_ATTACHMENT_UNUSED)
+ continue;
+
+ assert(a < cmd_state->pass->attachment_count);
+ if (cmd_state->attachments[a].pending_clear_aspects) {
+ return true;
+ }
+ }
+
+ if (ds != VK_ATTACHMENT_UNUSED) {
+ assert(ds < cmd_state->pass->attachment_count);
+ if (cmd_state->attachments[ds].pending_clear_aspects)
+ return true;
+ }
+
+ return false;
+}
+
+void
+anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer)
+{
+ const struct anv_cmd_state *cmd_state = &cmd_buffer->state;
+ const VkRect2D render_area = cmd_buffer->state.render_area;
+
+
+ if (!subpass_needs_clear(cmd_buffer))
+ return;
+
+ /* Because this gets called within a render pass, we tell blorp not to
+ * trash our depth and stencil buffers.
+ */
+ struct blorp_batch batch;
+ blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer,
+ BLORP_BATCH_NO_EMIT_DEPTH_STENCIL);
+
+ VkClearRect clear_rect = {
+ .rect = cmd_buffer->state.render_area,
+ .baseArrayLayer = 0,
+ .layerCount = cmd_buffer->state.framebuffer->layers,
+ };
+
+ struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
+ for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
+ const uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
+ if (a == VK_ATTACHMENT_UNUSED)
+ continue;
+
+ assert(a < cmd_state->pass->attachment_count);
+ struct anv_attachment_state *att_state = &cmd_state->attachments[a];
+
+ if (!att_state->pending_clear_aspects)
+ continue;
+
+ assert(att_state->pending_clear_aspects == VK_IMAGE_ASPECT_COLOR_BIT);
+
+ struct anv_image_view *iview = fb->attachments[a];
+ const struct anv_image *image = iview->image;
+ struct blorp_surf surf;
+ get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
+ att_state->aux_usage, &surf);
+
+ if (att_state->fast_clear) {
+ surf.clear_color = vk_to_isl_color(att_state->clear_value.color);
+
+ /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
+ *
+ * "After Render target fast clear, pipe-control with color cache
+ * write-flush must be issued before sending any DRAW commands on
+ * that render target."
+ *
+ * This comment is a bit cryptic and doesn't really tell you what's
+ * going or what's really needed. It appears that fast clear ops are
+ * not properly synchronized with other drawing. This means that we
+ * cannot have a fast clear operation in the pipe at the same time as
+ * other regular drawing operations. We need to use a PIPE_CONTROL
+ * to ensure that the contents of the previous draw hit the render
+ * target before we resolve and then use a second PIPE_CONTROL after
+ * the resolve to ensure that it is completed before any additional
+ * drawing occurs.
+ */
+ cmd_buffer->state.pending_pipe_bits |=
+ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
+
+ blorp_fast_clear(&batch, &surf, iview->isl.format,
+ iview->isl.base_level,
+ iview->isl.base_array_layer, fb->layers,
+ render_area.offset.x, render_area.offset.y,
+ render_area.offset.x + render_area.extent.width,
+ render_area.offset.y + render_area.extent.height);
+
+ cmd_buffer->state.pending_pipe_bits |=
+ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
+ } else {
+ blorp_clear(&batch, &surf, iview->isl.format,
+ anv_swizzle_for_render(iview->isl.swizzle),
+ iview->isl.base_level,
+ iview->isl.base_array_layer, fb->layers,
+ render_area.offset.x, render_area.offset.y,
+ render_area.offset.x + render_area.extent.width,
+ render_area.offset.y + render_area.extent.height,
+ vk_to_isl_color(att_state->clear_value.color), NULL);
+ }
+
+ att_state->pending_clear_aspects = 0;
+ }
+
+ const uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
+ assert(ds == VK_ATTACHMENT_UNUSED || ds < cmd_state->pass->attachment_count);
+
+ if (ds != VK_ATTACHMENT_UNUSED &&
+ cmd_state->attachments[ds].pending_clear_aspects) {
+
+ VkClearAttachment clear_att = {
+ .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
+ .clearValue = cmd_state->attachments[ds].clear_value,
+ };
+
+
+ const uint8_t gen = cmd_buffer->device->info.gen;
+ bool clear_with_hiz = gen >= 8 && cmd_state->attachments[ds].aux_usage ==
+ ISL_AUX_USAGE_HIZ;
+ const struct anv_image_view *iview = fb->attachments[ds];
+
+ if (clear_with_hiz) {
+ const bool clear_depth = clear_att.aspectMask &
+ VK_IMAGE_ASPECT_DEPTH_BIT;
+ const bool clear_stencil = clear_att.aspectMask &
+ VK_IMAGE_ASPECT_STENCIL_BIT;
+
+ /* Check against restrictions for depth buffer clearing. A great GPU
+ * performance benefit isn't expected when using the HZ sequence for
+ * stencil-only clears. Therefore, we don't emit a HZ op sequence for
+ * a stencil clear in addition to using the BLORP-fallback for depth.
+ */
+ if (clear_depth) {
+ if (!blorp_can_hiz_clear_depth(gen, iview->isl.format,
+ iview->image->samples,
+ render_area.offset.x,
+ render_area.offset.y,
+ render_area.offset.x +
+ render_area.extent.width,
+ render_area.offset.y +
+ render_area.extent.height)) {
+ clear_with_hiz = false;
+ } else if (clear_att.clearValue.depthStencil.depth !=
+ ANV_HZ_FC_VAL) {
+ /* Don't enable fast depth clears for any color not equal to
+ * ANV_HZ_FC_VAL.
+ */
+ clear_with_hiz = false;
+ } else if (gen == 8 &&
+ anv_can_sample_with_hiz(&cmd_buffer->device->info,
+ iview->aspect_mask,
+ iview->image->samples)) {
+ /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
+ * fast-cleared portion of a HiZ buffer. Testing has revealed
+ * that Gen8 only supports returning 0.0f. Gens prior to gen8 do
+ * not support this feature at all.
+ */
+ clear_with_hiz = false;
+ }
+ }
+
+ if (clear_with_hiz) {
+ blorp_gen8_hiz_clear_attachments(&batch, iview->image->samples,
+ render_area.offset.x,
+ render_area.offset.y,
+ render_area.offset.x +
+ render_area.extent.width,
+ render_area.offset.y +
+ render_area.extent.height,
+ clear_depth, clear_stencil,
+ clear_att.clearValue.
+ depthStencil.stencil);
+
+ /* From the SKL PRM, Depth Buffer Clear:
+ *
+ * Depth Buffer Clear Workaround
+ * Depth buffer clear pass using any of the methods (WM_STATE,
+ * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
+ * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
+ * “set” before starting to render. DepthStall and DepthFlush are
+ * not needed between consecutive depth clear passes nor is it
+ * required if the depth-clear pass was done with “full_surf_clear”
+ * bit set in the 3DSTATE_WM_HZ_OP.
+ */
+ if (clear_depth) {
+ cmd_buffer->state.pending_pipe_bits |=
+ ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_DEPTH_STALL_BIT;
+ }
+ }
+ }
+
+ if (!clear_with_hiz) {
+ clear_depth_stencil_attachment(cmd_buffer, &batch,
+ &clear_att, 1, &clear_rect);
+ }
+
+ cmd_state->attachments[ds].pending_clear_aspects = 0;
+ }
+
+ blorp_batch_finish(&batch);
+}
+