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winsys/amdgpu: avoid ioctl call when fence_wait is called without timeout
[mesa.git]
/
src
/
intel
/
vulkan
/
anv_meta_blit2d.c
diff --git
a/src/intel/vulkan/anv_meta_blit2d.c
b/src/intel/vulkan/anv_meta_blit2d.c
index 5c1e30c12ac500dbbe6d20ec2500d1556b0ea978..06e104329527e77b80bb78d08482a11fc060f045 100644
(file)
--- a/
src/intel/vulkan/anv_meta_blit2d.c
+++ b/
src/intel/vulkan/anv_meta_blit2d.c
@@
-1010,9
+1010,7
@@
build_nir_w_tiled_fragment_shader(struct anv_device *device,
discard->src[0] = nir_src_for_ssa(oob);
nir_builder_instr_insert(&b, &discard->instr);
discard->src[0] = nir_src_for_ssa(oob);
nir_builder_instr_insert(&b, &discard->instr);
- unsigned swiz[4] = { 0, 1, 0, 0 };
- nir_ssa_def *tex_off =
- nir_swizzle(&b, nir_load_var(&b, tex_off_in), swiz, 2, false);
+ nir_ssa_def *tex_off = nir_channels(&b, nir_load_var(&b, tex_off_in), 0x3);
nir_ssa_def *tex_pos = nir_iadd(&b, nir_vec2(&b, x_W, y_W), tex_off);
nir_ssa_def *tex_pitch = nir_channel(&b, nir_load_var(&b, tex_off_in), 2);
nir_ssa_def *tex_pos = nir_iadd(&b, nir_vec2(&b, x_W, y_W), tex_off);
nir_ssa_def *tex_pitch = nir_channel(&b, nir_load_var(&b, tex_off_in), 2);
@@
-1190,7
+1188,6
@@
blit2d_init_pipeline(struct anv_device *device,
const struct anv_graphics_pipeline_create_info anv_pipeline_info = {
.color_attachment_count = -1,
.use_repclear = false,
const struct anv_graphics_pipeline_create_info anv_pipeline_info = {
.color_attachment_count = -1,
.use_repclear = false,
- .disable_scissor = true,
.disable_vs = true,
.use_rectlist = true
};
.disable_vs = true,
.use_rectlist = true
};