-
- const uint32_t slm_size = encode_slm_size(GEN_GEN, prog_data->total_shared);
-
- struct anv_state state =
- anv_state_pool_emit(&device->dynamic_state_pool,
- GENX(INTERFACE_DESCRIPTOR_DATA), 64,
- .KernelStartPointer = pipeline->cs_simd,
- .KernelStartPointerHigh = 0,
- .BindingTablePointer = surfaces.offset,
- .BindingTableEntryCount = 0,
- .SamplerStatePointer = samplers.offset,
- .SamplerCount = 0,
- .ConstantIndirectURBEntryReadLength =
- cs_prog_data->push.per_thread.regs,
- .ConstantURBEntryReadOffset = 0,
- .BarrierEnable = cs_prog_data->uses_barrier,
- .SharedLocalMemorySize = slm_size,
- .NumberofThreadsinGPGPUThreadGroup =
- cs_prog_data->threads,
- .CrossThreadConstantDataReadLength =
- cs_prog_data->push.cross_thread.regs);
-
- uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
- anv_batch_emit(&cmd_buffer->batch,
- GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), mid) {
- mid.InterfaceDescriptorTotalLength = size;
- mid.InterfaceDescriptorDataStartAddress = state.offset;
- }
-
- return VK_SUCCESS;
-}
-
-void
-genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
-{
- struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
- MAYBE_UNUSED VkResult result;
-
- assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
-
- genX(cmd_buffer_config_l3)(cmd_buffer, pipeline->urb.l3_config);
-
- genX(flush_pipeline_select_gpgpu)(cmd_buffer);
-
- if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
- anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
-
- if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
- (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
- result = flush_compute_descriptor_set(cmd_buffer);
- assert(result == VK_SUCCESS);
- cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
- }
-
- cmd_buffer->state.compute_dirty = 0;
-
- genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
-}
-
-
-/**
- * Emit the HZ_OP packet in the sequence specified by the BDW PRM section
- * entitled: "Optimized Depth Buffer Clear and/or Stencil Buffer Clear."
- *
- * \todo Enable Stencil Buffer-only clears
- */
-void
-genX(cmd_buffer_emit_hz_op)(struct anv_cmd_buffer *cmd_buffer,
- enum blorp_hiz_op op)
-{
- struct anv_cmd_state *cmd_state = &cmd_buffer->state;
- const struct anv_image_view *iview =
- anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
-
- if (iview == NULL || !anv_image_has_hiz(iview->image))
- return;
-
- /* FINISHME: Implement multi-subpass HiZ */
- if (cmd_buffer->state.pass->subpass_count > 1)
- return;
-
- const uint32_t ds = cmd_state->subpass->depth_stencil_attachment;
-
- /* Section 7.4. of the Vulkan 1.0.27 spec states:
- *
- * "The render area must be contained within the framebuffer dimensions."
- *
- * Therefore, the only way the extent of the render area can match that of
- * the image view is if the render area offset equals (0, 0).
- */
- const bool full_surface_op =
- cmd_state->render_area.extent.width == iview->extent.width &&
- cmd_state->render_area.extent.height == iview->extent.height;
- if (full_surface_op)
- assert(cmd_state->render_area.offset.x == 0 &&
- cmd_state->render_area.offset.y == 0);
-
- /* This variable corresponds to the Pixel Dim column in the table below */
- struct isl_extent2d px_dim;
-
- /* Validate that we can perform the HZ operation and that it's necessary. */
- switch (op) {
- case BLORP_HIZ_OP_DEPTH_CLEAR:
- if (cmd_buffer->state.pass->attachments[ds].load_op !=
- VK_ATTACHMENT_LOAD_OP_CLEAR)
- return;
-
- /* Apply alignment restrictions. Despite the BDW PRM mentioning this is
- * only needed for a depth buffer surface type of D16_UNORM, testing
- * showed it to be necessary for other depth formats as well
- * (e.g., D32_FLOAT).
- */
-#if GEN_GEN == 8
- /* Pre-SKL, HiZ has an 8x4 sample block. As the number of samples
- * increases, the number of pixels representable by this block
- * decreases by a factor of the sample dimensions. Sample dimensions
- * scale following the MSAA interleaved pattern.
- *
- * Sample|Sample|Pixel
- * Count |Dim |Dim
- * ===================
- * 1 | 1x1 | 8x4
- * 2 | 2x1 | 4x4
- * 4 | 2x2 | 4x2
- * 8 | 4x2 | 2x2
- * 16 | 4x4 | 2x1
- *
- * Table: Pixel Dimensions in a HiZ Sample Block Pre-SKL
- */
- /* This variable corresponds to the Sample Dim column in the table
- * above.
- */
- const struct isl_extent2d sa_dim =
- isl_get_interleaved_msaa_px_size_sa(iview->image->samples);
- px_dim.w = 8 / sa_dim.w;
- px_dim.h = 4 / sa_dim.h;
-#elif GEN_GEN >= 9
- /* SKL+, the sample block becomes a "pixel block" so the expected
- * pixel dimension is a constant 8x4 px for all sample counts.
- */
- px_dim = (struct isl_extent2d) { .w = 8, .h = 4};