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x86: changes to apic, keyboard
[gem5.git]
/
src
/
mem
/
SConscript
diff --git
a/src/mem/SConscript
b/src/mem/SConscript
index 50423fa67dd5c5e0d92b4305eb741bba797e738b..ca89418b54ebd8d3a0bc8619ef2d58221755f608 100644
(file)
--- a/
src/mem/SConscript
+++ b/
src/mem/SConscript
@@
-30,35
+30,57
@@
Import('*')
Import('*')
+# Only build the communication if we have support for protobuf as the
+# tracing relies on it
+if env['HAVE_PROTOBUF']:
+ SimObject('CommMonitor.py')
+ Source('comm_monitor.cc')
+
+SimObject('AddrMapper.py')
SimObject('Bridge.py')
SimObject('Bus.py')
SimObject('MemObject.py')
SimObject('Bridge.py')
SimObject('Bus.py')
SimObject('MemObject.py')
+Source('addr_mapper.cc')
Source('bridge.cc')
Source('bus.cc')
Source('bridge.cc')
Source('bus.cc')
+Source('coherent_bus.cc')
Source('mem_object.cc')
Source('mem_object.cc')
+Source('mport.cc')
+Source('noncoherent_bus.cc')
Source('packet.cc')
Source('port.cc')
Source('packet.cc')
Source('port.cc')
+Source('packet_queue.cc')
Source('tport.cc')
Source('tport.cc')
-Source('mport.cc')
+Source('port_proxy.cc')
+Source('fs_translating_port_proxy.cc')
+Source('se_translating_port_proxy.cc')
if env['TARGET_ISA'] != 'no':
if env['TARGET_ISA'] != 'no':
- SimObject('PhysicalMemory.py')
- Source('dram.cc')
- Source('physical.cc')
-
-if env['FULL_SYSTEM']:
- Source('vport.cc')
-elif env['TARGET_ISA'] != 'no':
+ SimObject('AbstractMemory.py')
+ SimObject('SimpleMemory.py')
+ SimObject('SimpleDRAM.py')
+ Source('abstract_mem.cc')
+ Source('simple_mem.cc')
Source('page_table.cc')
Source('page_table.cc')
- Source('translating_port.cc')
+ Source('physical.cc')
+ Source('simple_dram.cc')
-DebugFlag('Bus')
+DebugFlag('B
aseB
us')
DebugFlag('BusAddrRanges')
DebugFlag('BusAddrRanges')
-DebugFlag('BusBridge')
+DebugFlag('CoherentBus')
+DebugFlag('NoncoherentBus')
+CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus',
+ 'NoncoherentBus'])
+
+DebugFlag('Bridge')
+DebugFlag('CommMonitor')
+DebugFlag('DRAM')
+DebugFlag('DRAMWR')
DebugFlag('LLSC')
DebugFlag('MMU')
DebugFlag('MemoryAccess')
DebugFlag('LLSC')
DebugFlag('MMU')
DebugFlag('MemoryAccess')
+DebugFlag('PacketQueue')
DebugFlag('ProtocolTrace')
DebugFlag('RubyCache')
DebugFlag('ProtocolTrace')
DebugFlag('RubyCache')
@@
-68,12
+90,16
@@
DebugFlag('RubyGenerated')
DebugFlag('RubyMemory')
DebugFlag('RubyNetwork')
DebugFlag('RubyPort')
DebugFlag('RubyMemory')
DebugFlag('RubyNetwork')
DebugFlag('RubyPort')
+DebugFlag('RubyPrefetcher')
DebugFlag('RubyQueue')
DebugFlag('RubySequencer')
DebugFlag('RubySlicc')
DebugFlag('RubySystem')
DebugFlag('RubyTester')
DebugFlag('RubyQueue')
DebugFlag('RubySequencer')
DebugFlag('RubySlicc')
DebugFlag('RubySystem')
DebugFlag('RubyTester')
+DebugFlag('RubyStats')
+DebugFlag('RubyResourceStalls')
CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
'RubyGenerated', 'RubySlicc', 'RubySystem', 'RubyCache',
CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
'RubyGenerated', 'RubySlicc', 'RubySystem', 'RubyCache',
- 'RubyMemory', 'RubyDma', 'RubyPort', 'RubySequencer', 'RubyCacheTrace'])
+ 'RubyMemory', 'RubyDma', 'RubyPort', 'RubySequencer', 'RubyCacheTrace',
+ 'RubyPrefetcher'])