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x86: changes to apic, keyboard
[gem5.git]
/
src
/
mem
/
SConscript
diff --git
a/src/mem/SConscript
b/src/mem/SConscript
index d290da8752af8281f8d578b3d7a9aa4bab6fe758..ca89418b54ebd8d3a0bc8619ef2d58221755f608 100644
(file)
--- a/
src/mem/SConscript
+++ b/
src/mem/SConscript
@@
-30,15
+30,21
@@
Import('*')
Import('*')
+# Only build the communication if we have support for protobuf as the
+# tracing relies on it
+if env['HAVE_PROTOBUF']:
+ SimObject('CommMonitor.py')
+ Source('comm_monitor.cc')
+
+SimObject('AddrMapper.py')
SimObject('Bridge.py')
SimObject('Bus.py')
SimObject('Bridge.py')
SimObject('Bus.py')
-SimObject('CommMonitor.py')
SimObject('MemObject.py')
SimObject('MemObject.py')
+Source('addr_mapper.cc')
Source('bridge.cc')
Source('bus.cc')
Source('coherent_bus.cc')
Source('bridge.cc')
Source('bus.cc')
Source('coherent_bus.cc')
-Source('comm_monitor.cc')
Source('mem_object.cc')
Source('mport.cc')
Source('noncoherent_bus.cc')
Source('mem_object.cc')
Source('mport.cc')
Source('noncoherent_bus.cc')
@@
-53,10
+59,12
@@
Source('se_translating_port_proxy.cc')
if env['TARGET_ISA'] != 'no':
SimObject('AbstractMemory.py')
SimObject('SimpleMemory.py')
if env['TARGET_ISA'] != 'no':
SimObject('AbstractMemory.py')
SimObject('SimpleMemory.py')
+ SimObject('SimpleDRAM.py')
Source('abstract_mem.cc')
Source('simple_mem.cc')
Source('page_table.cc')
Source('physical.cc')
Source('abstract_mem.cc')
Source('simple_mem.cc')
Source('page_table.cc')
Source('physical.cc')
+ Source('simple_dram.cc')
DebugFlag('BaseBus')
DebugFlag('BusAddrRanges')
DebugFlag('BaseBus')
DebugFlag('BusAddrRanges')
@@
-65,8
+73,10
@@
DebugFlag('NoncoherentBus')
CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus',
'NoncoherentBus'])
CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus',
'NoncoherentBus'])
-DebugFlag('B
usB
ridge')
+DebugFlag('Bridge')
DebugFlag('CommMonitor')
DebugFlag('CommMonitor')
+DebugFlag('DRAM')
+DebugFlag('DRAMWR')
DebugFlag('LLSC')
DebugFlag('MMU')
DebugFlag('MemoryAccess')
DebugFlag('LLSC')
DebugFlag('MMU')
DebugFlag('MemoryAccess')
@@
-80,6
+90,7
@@
DebugFlag('RubyGenerated')
DebugFlag('RubyMemory')
DebugFlag('RubyNetwork')
DebugFlag('RubyPort')
DebugFlag('RubyMemory')
DebugFlag('RubyNetwork')
DebugFlag('RubyPort')
+DebugFlag('RubyPrefetcher')
DebugFlag('RubyQueue')
DebugFlag('RubySequencer')
DebugFlag('RubySlicc')
DebugFlag('RubyQueue')
DebugFlag('RubySequencer')
DebugFlag('RubySlicc')
@@
-90,4
+101,5
@@
DebugFlag('RubyResourceStalls')
CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
'RubyGenerated', 'RubySlicc', 'RubySystem', 'RubyCache',
CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
'RubyGenerated', 'RubySlicc', 'RubySystem', 'RubyCache',
- 'RubyMemory', 'RubyDma', 'RubyPort', 'RubySequencer', 'RubyCacheTrace'])
+ 'RubyMemory', 'RubyDma', 'RubyPort', 'RubySequencer', 'RubyCacheTrace',
+ 'RubyPrefetcher'])