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Merge zizzer.eecs.umich.edu:/bk/newmem/
[gem5.git]
/
src
/
mem
/
bus.hh
diff --git
a/src/mem/bus.hh
b/src/mem/bus.hh
index 27624b3780c0005e48c1e06f497abe25825ce211..ff1d2545d7be9aa5ebbade4c573872d34ba9dff9 100644
(file)
--- a/
src/mem/bus.hh
+++ b/
src/mem/bus.hh
@@
-242,6
+242,9
@@
class Bus : public MemObject
/** Port that handles requests that don't match any of the interfaces.*/
BusPort *defaultPort;
/** Port that handles requests that don't match any of the interfaces.*/
BusPort *defaultPort;
+ /** Has the user specified their own default responder? */
+ bool responderSet;
+
public:
/** A function used to return the port associated with this bus object. */
public:
/** A function used to return the port associated with this bus object. */
@@
-251,9
+254,11
@@
class Bus : public MemObject
unsigned int drain(Event *de);
unsigned int drain(Event *de);
- Bus(const std::string &n, int bus_id, int _clock, int _width)
+ Bus(const std::string &n, int bus_id, int _clock, int _width,
+ bool responder_set)
: MemObject(n), busId(bus_id), clock(_clock), width(_width),
: MemObject(n), busId(bus_id), clock(_clock), width(_width),
- tickNextIdle(0), busIdle(this), inRetry(false), defaultPort(NULL)
+ tickNextIdle(0), drainEvent(NULL), busIdle(this), inRetry(false),
+ defaultPort(NULL), responderSet(responder_set)
{
//Both the width and clock period must be positive
if (width <= 0)
{
//Both the width and clock period must be positive
if (width <= 0)