+ return clusivity == Enums::mostly_incl ||
+ cmd == MemCmd::WriteLineReq ||
+ cmd == MemCmd::ReadReq ||
+ cmd == MemCmd::WriteReq ||
+ cmd.isPrefetch() ||
+ cmd.isLLSC();
+ }
+
+ /**
+ * Regenerate block address using tags.
+ * Block address regeneration depends on whether we're using a temporary
+ * block or not.
+ *
+ * @param blk The block to regenerate address.
+ * @return The block's address.
+ */
+ Addr regenerateBlkAddr(CacheBlk* blk);
+
+ /**
+ * Calculate latency of accesses that only touch the tag array.
+ * @sa calculateAccessLatency
+ *
+ * @param delay The delay until the packet's metadata is present.
+ * @param lookup_lat Latency of the respective tag lookup.
+ * @return The number of ticks that pass due to a tag-only access.
+ */
+ Cycles calculateTagOnlyLatency(const uint32_t delay,
+ const Cycles lookup_lat) const;
+ /**
+ * Calculate access latency in ticks given a tag lookup latency, and
+ * whether access was a hit or miss.
+ *
+ * @param blk The cache block that was accessed.
+ * @param delay The delay until the packet's metadata is present.
+ * @param lookup_lat Latency of the respective tag lookup.
+ * @return The number of ticks that pass due to a block access.
+ */
+ Cycles calculateAccessLatency(const CacheBlk* blk, const uint32_t delay,
+ const Cycles lookup_lat) const;
+
+ /**
+ * Does all the processing necessary to perform the provided request.
+ * @param pkt The memory request to perform.
+ * @param blk The cache block to be updated.
+ * @param lat The latency of the access.
+ * @param writebacks List for any writebacks that need to be performed.
+ * @return Boolean indicating whether the request was satisfied.
+ */
+ virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
+ PacketList &writebacks);
+
+ /*
+ * Handle a timing request that hit in the cache
+ *
+ * @param ptk The request packet
+ * @param blk The referenced block
+ * @param request_time The tick at which the block lookup is compete
+ */
+ virtual void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
+ Tick request_time);
+
+ /*
+ * Handle a timing request that missed in the cache
+ *
+ * Implementation specific handling for different cache
+ * implementations
+ *
+ * @param ptk The request packet
+ * @param blk The referenced block
+ * @param forward_time The tick at which we can process dependent requests
+ * @param request_time The tick at which the block lookup is compete
+ */
+ virtual void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
+ Tick forward_time,
+ Tick request_time) = 0;
+
+ /*
+ * Handle a timing request that missed in the cache
+ *
+ * Common functionality across different cache implementations
+ *
+ * @param ptk The request packet
+ * @param blk The referenced block
+ * @param mshr Any existing mshr for the referenced cache block
+ * @param forward_time The tick at which we can process dependent requests
+ * @param request_time The tick at which the block lookup is compete
+ */
+ void handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk,
+ Tick forward_time, Tick request_time);
+
+ /**
+ * Performs the access specified by the request.
+ * @param pkt The request to perform.
+ */
+ virtual void recvTimingReq(PacketPtr pkt);
+
+ /**
+ * Handling the special case of uncacheable write responses to
+ * make recvTimingResp less cluttered.
+ */
+ void handleUncacheableWriteResp(PacketPtr pkt);
+
+ /**
+ * Service non-deferred MSHR targets using the received response
+ *
+ * Iterates through the list of targets that can be serviced with
+ * the current response.
+ *
+ * @param mshr The MSHR that corresponds to the reponse
+ * @param pkt The response packet
+ * @param blk The reference block
+ */
+ virtual void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
+ CacheBlk *blk) = 0;
+
+ /**
+ * Handles a response (cache line fill/write ack) from the bus.
+ * @param pkt The response packet
+ */
+ virtual void recvTimingResp(PacketPtr pkt);
+
+ /**
+ * Snoops bus transactions to maintain coherence.
+ * @param pkt The current bus transaction.
+ */
+ virtual void recvTimingSnoopReq(PacketPtr pkt) = 0;
+
+ /**
+ * Handle a snoop response.
+ * @param pkt Snoop response packet
+ */
+ virtual void recvTimingSnoopResp(PacketPtr pkt) = 0;
+
+ /**
+ * Handle a request in atomic mode that missed in this cache
+ *
+ * Creates a downstream request, sends it to the memory below and
+ * handles the response. As we are in atomic mode all operations
+ * are performed immediately.
+ *
+ * @param pkt The packet with the requests
+ * @param blk The referenced block
+ * @param writebacks A list with packets for any performed writebacks
+ * @return Cycles for handling the request
+ */
+ virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
+ PacketList &writebacks) = 0;
+
+ /**
+ * Performs the access specified by the request.
+ * @param pkt The request to perform.
+ * @return The number of ticks required for the access.
+ */
+ virtual Tick recvAtomic(PacketPtr pkt);
+
+ /**
+ * Snoop for the provided request in the cache and return the estimated
+ * time taken.
+ * @param pkt The memory request to snoop
+ * @return The number of ticks required for the snoop.
+ */
+ virtual Tick recvAtomicSnoop(PacketPtr pkt) = 0;
+
+ /**
+ * Performs the access specified by the request.
+ *
+ * @param pkt The request to perform.
+ * @param fromCpuSide from the CPU side port or the memory side port
+ */
+ virtual void functionalAccess(PacketPtr pkt, bool from_cpu_side);
+
+ /**
+ * Handle doing the Compare and Swap function for SPARC.
+ */
+ void cmpAndSwap(CacheBlk *blk, PacketPtr pkt);
+
+ /**
+ * Return the next queue entry to service, either a pending miss
+ * from the MSHR queue, a buffered write from the write buffer, or
+ * something from the prefetcher. This function is responsible
+ * for prioritizing among those sources on the fly.
+ */
+ QueueEntry* getNextQueueEntry();
+
+ /**
+ * Insert writebacks into the write buffer
+ */
+ virtual void doWritebacks(PacketList& writebacks, Tick forward_time) = 0;
+
+ /**
+ * Send writebacks down the memory hierarchy in atomic mode
+ */
+ virtual void doWritebacksAtomic(PacketList& writebacks) = 0;
+
+ /**
+ * Create an appropriate downstream bus request packet.
+ *
+ * Creates a new packet with the request to be send to the memory
+ * below, or nullptr if the current request in cpu_pkt should just
+ * be forwarded on.
+ *
+ * @param cpu_pkt The miss packet that needs to be satisfied.
+ * @param blk The referenced block, can be nullptr.
+ * @param needs_writable Indicates that the block must be writable
+ * even if the request in cpu_pkt doesn't indicate that.
+ * @param is_whole_line_write True if there are writes for the
+ * whole line
+ * @return A packet send to the memory below
+ */
+ virtual PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
+ bool needs_writable,
+ bool is_whole_line_write) const = 0;
+
+ /**
+ * Determine if clean lines should be written back or not. In
+ * cases where a downstream cache is mostly inclusive we likely
+ * want it to act as a victim cache also for lines that have not
+ * been modified. Hence, we cannot simply drop the line (or send a
+ * clean evict), but rather need to send the actual data.
+ */
+ const bool writebackClean;
+
+ /**
+ * Writebacks from the tempBlock, resulting on the response path
+ * in atomic mode, must happen after the call to recvAtomic has
+ * finished (for the right ordering of the packets). We therefore
+ * need to hold on to the packets, and have a method and an event
+ * to send them.
+ */
+ PacketPtr tempBlockWriteback;
+
+ /**
+ * Send the outstanding tempBlock writeback. To be called after
+ * recvAtomic finishes in cases where the block we filled is in
+ * fact the tempBlock, and now needs to be written back.
+ */
+ void writebackTempBlockAtomic() {
+ assert(tempBlockWriteback != nullptr);
+ PacketList writebacks{tempBlockWriteback};
+ doWritebacksAtomic(writebacks);
+ tempBlockWriteback = nullptr;