+ class CpuSidePort : public CachePort
+ {
+ public:
+ CpuSidePort(const std::string &_name,
+ Cache<TagStore,Coherence> *_cache);
+
+ // BaseCache::CachePort just has a BaseCache *; this function
+ // lets us get back the type info we lost when we stored the
+ // cache pointer there.
+ Cache<TagStore,Coherence> *myCache() {
+ return static_cast<Cache<TagStore,Coherence> *>(cache);
+ }
+
+ virtual void getDeviceAddressRanges(AddrRangeList &resp,
+ bool &snoop);
+
+ virtual bool recvTiming(PacketPtr pkt);
+
+ virtual Tick recvAtomic(PacketPtr pkt);
+
+ virtual void recvFunctional(PacketPtr pkt);
+ };
+
+ class MemSidePort : public CachePort
+ {
+ public:
+ MemSidePort(const std::string &_name,
+ Cache<TagStore,Coherence> *_cache);
+
+ // BaseCache::CachePort just has a BaseCache *; this function
+ // lets us get back the type info we lost when we stored the
+ // cache pointer there.
+ Cache<TagStore,Coherence> *myCache() {
+ return static_cast<Cache<TagStore,Coherence> *>(cache);
+ }
+
+ void sendPacket();
+
+ void processSendEvent();
+
+ virtual void getDeviceAddressRanges(AddrRangeList &resp,
+ bool &snoop);
+
+ virtual bool recvTiming(PacketPtr pkt);
+
+ virtual void recvRetry();
+
+ virtual Tick recvAtomic(PacketPtr pkt);
+
+ virtual void recvFunctional(PacketPtr pkt);
+
+ typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
+ SendEvent;
+ };
+