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mem-cache: Fix set and way of sub-entries
[gem5.git]
/
src
/
mem
/
cache
/
noncoherent_cache.cc
diff --git
a/src/mem/cache/noncoherent_cache.cc
b/src/mem/cache/noncoherent_cache.cc
index 50738375e68607b819441ad9e9b7f1c3608126d6..9a2a1db9d85a3c412e3d380b31e06eefc0c68dbb 100644
(file)
--- a/
src/mem/cache/noncoherent_cache.cc
+++ b/
src/mem/cache/noncoherent_cache.cc
@@
-60,7
+60,7
@@
#include "base/trace.hh"
#include "base/types.hh"
#include "debug/Cache.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "debug/Cache.hh"
-#include "mem/cache/blk.hh"
+#include "mem/cache/
cache_
blk.hh"
#include "mem/cache/mshr.hh"
#include "params/NoncoherentCache.hh"
#include "mem/cache/mshr.hh"
#include "params/NoncoherentCache.hh"
@@
-148,7
+148,8
@@
NoncoherentCache::recvTimingReq(PacketPtr pkt)
PacketPtr
NoncoherentCache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
PacketPtr
NoncoherentCache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
- bool needs_writable) const
+ bool needs_writable,
+ bool is_whole_line_write) const
{
// We also fill for writebacks from the coherent caches above us,
// and they do not need responses
{
// We also fill for writebacks from the coherent caches above us,
// and they do not need responses
@@
-170,10
+171,11
@@
NoncoherentCache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
Cycles
Cycles
-NoncoherentCache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk,
+NoncoherentCache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *
&
blk,
PacketList &writebacks)
{
PacketList &writebacks)
{
- PacketPtr bus_pkt = createMissPacket(pkt, blk, true);
+ PacketPtr bus_pkt = createMissPacket(pkt, blk, true,
+ pkt->isWholeLineWrite(blkSize));
DPRINTF(Cache, "Sending an atomic %s\n", bus_pkt->print());
Cycles latency = ticksToCycles(memSidePort.sendAtomic(bus_pkt));
DPRINTF(Cache, "Sending an atomic %s\n", bus_pkt->print());
Cycles latency = ticksToCycles(memSidePort.sendAtomic(bus_pkt));
@@
-241,11
+243,10
@@
NoncoherentCache::functionalAccess(PacketPtr pkt, bool from_cpu_side)
void
NoncoherentCache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
void
NoncoherentCache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
- CacheBlk *blk
, PacketList &writebacks
)
+ CacheBlk *blk)
{
{
- MSHR::Target *initial_tgt = mshr->getTarget();
// First offset for critical word first calculations
// First offset for critical word first calculations
- const int initial_offset =
initial_tgt
->pkt->getOffset(blkSize);
+ const int initial_offset =
mshr->getTarget()
->pkt->getOffset(blkSize);
MSHR::TargetList targets = mshr->extractServiceableTargets(pkt);
for (auto &target: targets) {
MSHR::TargetList targets = mshr->extractServiceableTargets(pkt);
for (auto &target: targets) {
@@
-286,7
+287,7
@@
NoncoherentCache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
// Reset the bus additional time as it is now accounted for
tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0;
// Reset the bus additional time as it is now accounted for
tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0;
- cpuSidePort.schedTimingResp(tgt_pkt, completion_time
, true
);
+ cpuSidePort.schedTimingResp(tgt_pkt, completion_time);
break;
case MSHR::Target::FromPrefetcher:
break;
case MSHR::Target::FromPrefetcher:
@@
-355,15
+356,6
@@
NoncoherentCache::evictBlock(CacheBlk *blk)
return pkt;
}
return pkt;
}
-void
-NoncoherentCache::evictBlock(CacheBlk *blk, PacketList &writebacks)
-{
- PacketPtr pkt = evictBlock(blk);
- if (pkt) {
- writebacks.push_back(pkt);
- }
-}
-
NoncoherentCache*
NoncoherentCacheParams::create()
{
NoncoherentCache*
NoncoherentCacheParams::create()
{