-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DRAMMemory)
-
- Param<std::string> file;
- Param<Range<Addr> > range;
- Param<Tick> latency;
- /* additional params for dram protocol*/
- Param<int> cpu_ratio;
- Param<std::string> mem_type;
- Param<std::string> mem_actpolicy;
- Param<std::string> memctrladdr_type;
- Param<int> bus_width;
- Param<int> act_lat;
- Param<int> cas_lat;
- Param<int> war_lat;
- Param<int> pre_lat;
- Param<int> dpl_lat;
- Param<int> trc_lat;
- Param<int> num_banks;
- Param<int> num_cpus;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DRAMMemory)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DRAMMemory)
-
- INIT_PARAM_DFLT(file, "memory mapped file", ""),
- INIT_PARAM(range, "Device Address Range"),
- INIT_PARAM(latency, "Memory access latency"),
-
- /* additional params for dram protocol*/
- INIT_PARAM_DFLT(cpu_ratio,"ratio between CPU speed and memory bus speed",5),
- INIT_PARAM_DFLT(mem_type,"type of DRAM","SDRAM"),
- INIT_PARAM_DFLT(mem_actpolicy,"open / closed page policy","open"),
- INIT_PARAM_DFLT(memctrladdr_type,"interleaved or direct mapping","interleaved"),
- INIT_PARAM_DFLT(bus_width,"memory access bus width",16),
- INIT_PARAM_DFLT(act_lat,"RAS to CAS delay",2),
- INIT_PARAM_DFLT(cas_lat,"CAS delay",1),
- INIT_PARAM_DFLT(war_lat,"write after read delay",2),
- INIT_PARAM_DFLT(pre_lat,"precharge delay",2),
- INIT_PARAM_DFLT(dpl_lat,"data in to precharge delay",2),
- INIT_PARAM_DFLT(trc_lat,"row cycle delay",6),
- INIT_PARAM_DFLT(num_banks,"Number of Banks",4),
- INIT_PARAM_DFLT(num_cpus,"Number of CPUs connected to DRAM",4)
-
-END_INIT_SIM_OBJECT_PARAMS(DRAMMemory)
-
-CREATE_SIM_OBJECT(DRAMMemory)