- Stats::Vector<> accesses;
- Stats::Vector<> bytesRequested;
- Stats::Vector<> bytesSent;
- Stats::Vector<> compressedAccesses;
-
- Stats::Vector<> cycles_nCKE;
- Stats::Vector<> cycles_all_precharge_CKE;
- Stats::Vector<> cycles_all_precharge_nCKE;
- Stats::Vector<> cycles_bank_active_nCKE;
- Stats::Vector<> cycles_avg_ACT;
- Stats::Vector<> cycles_read_out;
- Stats::Vector<> cycles_write_in;
- Stats::Vector<> cycles_between_misses;
- Stats::Vector<> other_bank_read_access_miss;
- Stats::Vector<> other_bank_write_access_miss;
- Stats::Scalar<> total_latency;
- Stats::Scalar<> total_icache_req;
- Stats::Scalar<> total_arb_latency;
+ Stats::Vector accesses;
+ Stats::Vector bytesRequested;
+ Stats::Vector bytesSent;
+ Stats::Vector compressedAccesses;
+
+ Stats::Vector cycles_nCKE;
+ Stats::Vector cycles_all_precharge_CKE;
+ Stats::Vector cycles_all_precharge_nCKE;
+ Stats::Vector cycles_bank_active_nCKE;
+ Stats::Vector cycles_avg_ACT;
+ Stats::Vector cycles_read_out;
+ Stats::Vector cycles_write_in;
+ Stats::Vector cycles_between_misses;
+ Stats::Vector other_bank_read_access_miss;
+ Stats::Vector other_bank_write_access_miss;
+ Stats::Scalar total_latency;
+ Stats::Scalar total_icache_req;
+ Stats::Scalar total_arb_latency;