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mem-cache: Fix non-virtual base destructor of Repl Entry
[gem5.git]
/
src
/
mem
/
protocol
/
MESI_Two_Level-L2cache.sm
diff --git
a/src/mem/protocol/MESI_Two_Level-L2cache.sm
b/src/mem/protocol/MESI_Two_Level-L2cache.sm
index e4f719d9f993779a0deb4ade3b6a58e9e4f093d8..5a8cfae6de89e4557f81efb13b21e0be55751d65 100644
(file)
--- a/
src/mem/protocol/MESI_Two_Level-L2cache.sm
+++ b/
src/mem/protocol/MESI_Two_Level-L2cache.sm
@@
-26,7
+26,7
@@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(L2Cache, "MESI Directory L2 Cache CMP")
+machine(
MachineType:
L2Cache, "MESI Directory L2 Cache CMP")
: CacheMemory * L2cache;
Cycles l2_request_latency := 2;
Cycles l2_response_latency := 2;
: CacheMemory * L2cache;
Cycles l2_request_latency := 2;
Cycles l2_response_latency := 2;
@@
-148,12
+148,17
@@
machine(L2Cache, "MESI Directory L2 Cache CMP")
TBETable TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
TBETable TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
+ Tick clockEdge();
+ Tick cyclesToTicks(Cycles c);
+ Cycles ticksToCycles(Tick t);
+
void set_cache_entry(AbstractCacheEntry a);
void unset_cache_entry();
void set_tbe(TBE a);
void unset_tbe();
void wakeUpBuffers(Addr a);
void profileMsgDelay(int virtualNetworkType, Cycles c);
void set_cache_entry(AbstractCacheEntry a);
void unset_cache_entry();
void set_tbe(TBE a);
void unset_tbe();
void wakeUpBuffers(Addr a);
void profileMsgDelay(int virtualNetworkType, Cycles c);
+ MachineID mapAddressToMachine(Addr addr, MachineType mtype);
// inclusive cache, returns L2 entries only
Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
// inclusive cache, returns L2 entries only
Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
@@
-170,7
+175,7
@@
machine(L2Cache, "MESI Directory L2 Cache CMP")
void addSharer(Addr addr, MachineID requestor, Entry cache_entry) {
assert(is_valid(cache_entry));
void addSharer(Addr addr, MachineID requestor, Entry cache_entry) {
assert(is_valid(cache_entry));
- DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %
s
\n",
+ DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %
#x
\n",
machineID, requestor, addr);
cache_entry.Sharers.add(requestor);
}
machineID, requestor, addr);
cache_entry.Sharers.add(requestor);
}
@@
-263,7
+268,7
@@
machine(L2Cache, "MESI Directory L2 Cache CMP")
return Event:L1_PUTX_old;
}
} else {
return Event:L1_PUTX_old;
}
} else {
- DPRINTF(RubySlicc, "address: %
s
, Request Type: %s\n", addr, type);
+ DPRINTF(RubySlicc, "address: %
#x
, Request Type: %s\n", addr, type);
error("Invalid L1 forwarded request type");
}
}
error("Invalid L1 forwarded request type");
}
}
@@
-285,11
+290,11
@@
machine(L2Cache, "MESI Directory L2 Cache CMP")
in_port(L1unblockNetwork_in, ResponseMsg, unblockToL2Cache, rank = 2) {
in_port(L1unblockNetwork_in, ResponseMsg, unblockToL2Cache, rank = 2) {
- if(L1unblockNetwork_in.isReady()) {
+ if(L1unblockNetwork_in.isReady(
clockEdge()
)) {
peek(L1unblockNetwork_in, ResponseMsg) {
Entry cache_entry := getCacheEntry(in_msg.addr);
TBE tbe := TBEs[in_msg.addr];
peek(L1unblockNetwork_in, ResponseMsg) {
Entry cache_entry := getCacheEntry(in_msg.addr);
TBE tbe := TBEs[in_msg.addr];
- DPRINTF(RubySlicc, "Addr: %
s
State: %s Sender: %s Type: %s Dest: %s\n",
+ DPRINTF(RubySlicc, "Addr: %
#x
State: %s Sender: %s Type: %s Dest: %s\n",
in_msg.addr, getState(tbe, cache_entry, in_msg.addr),
in_msg.Sender, in_msg.Type, in_msg.Destination);
in_msg.addr, getState(tbe, cache_entry, in_msg.addr),
in_msg.Sender, in_msg.Type, in_msg.Destination);
@@
-307,7
+312,7
@@
machine(L2Cache, "MESI Directory L2 Cache CMP")
// Response L2 Network - response msg to this particular L2 bank
in_port(responseL2Network_in, ResponseMsg, responseToL2Cache, rank = 1) {
// Response L2 Network - response msg to this particular L2 bank
in_port(responseL2Network_in, ResponseMsg, responseToL2Cache, rank = 1) {
- if (responseL2Network_in.isReady()) {
+ if (responseL2Network_in.isReady(
clockEdge()
)) {
peek(responseL2Network_in, ResponseMsg) {
// test wether it's from a local L1 or an off chip source
assert(in_msg.Destination.isElement(machineID));
peek(responseL2Network_in, ResponseMsg) {
// test wether it's from a local L1 or an off chip source
assert(in_msg.Destination.isElement(machineID));
@@
-348,12
+353,12
@@
machine(L2Cache, "MESI Directory L2 Cache CMP")
// L1 Request
in_port(L1RequestL2Network_in, RequestMsg, L1RequestToL2Cache, rank = 0) {
// L1 Request
in_port(L1RequestL2Network_in, RequestMsg, L1RequestToL2Cache, rank = 0) {
- if(L1RequestL2Network_in.isReady()) {
+ if(L1RequestL2Network_in.isReady(
clockEdge()
)) {
peek(L1RequestL2Network_in, RequestMsg) {
Entry cache_entry := getCacheEntry(in_msg.addr);
TBE tbe := TBEs[in_msg.addr];
peek(L1RequestL2Network_in, RequestMsg) {
Entry cache_entry := getCacheEntry(in_msg.addr);
TBE tbe := TBEs[in_msg.addr];
- DPRINTF(RubySlicc, "Addr: %
s
State: %s Req: %s Type: %s Dest: %s\n",
+ DPRINTF(RubySlicc, "Addr: %
#x
State: %s Req: %s Type: %s Dest: %s\n",
in_msg.addr, getState(tbe, cache_entry, in_msg.addr),
in_msg.Requestor, in_msg.Type, in_msg.Destination);
in_msg.addr, getState(tbe, cache_entry, in_msg.addr),
in_msg.Requestor, in_msg.Type, in_msg.Destination);
@@
-396,7
+401,7
@@
machine(L2Cache, "MESI Directory L2 Cache CMP")
out_msg.addr := address;
out_msg.Type := CoherenceRequestType:GETS;
out_msg.Requestor := machineID;
out_msg.addr := address;
out_msg.Type := CoherenceRequestType:GETS;
out_msg.Requestor := machineID;
- out_msg.Destination.add(map
_Address_to_Directory(address
));
+ out_msg.Destination.add(map
AddressToMachine(address, MachineType:Directory
));
out_msg.MessageSize := MessageSizeType:Control;
}
}
out_msg.MessageSize := MessageSizeType:Control;
}
}
@@
-421,7
+426,7
@@
machine(L2Cache, "MESI Directory L2 Cache CMP")
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:MEMORY_DATA;
out_msg.Sender := machineID;
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:MEMORY_DATA;
out_msg.Sender := machineID;
- out_msg.Destination.add(map
_Address_to_Directory(address
));
+ out_msg.Destination.add(map
AddressToMachine(address, MachineType:Directory
));
out_msg.DataBlk := cache_entry.DataBlk;
out_msg.Dirty := cache_entry.Dirty;
out_msg.MessageSize := MessageSizeType:Response_Data;
out_msg.DataBlk := cache_entry.DataBlk;
out_msg.Dirty := cache_entry.Dirty;
out_msg.MessageSize := MessageSizeType:Response_Data;
@@
-433,7
+438,7
@@
machine(L2Cache, "MESI Directory L2 Cache CMP")
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:ACK;
out_msg.Sender := machineID;
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:ACK;
out_msg.Sender := machineID;
- out_msg.Destination.add(map
_Address_to_Directory(address
));
+ out_msg.Destination.add(map
AddressToMachine(address, MachineType:Directory
));
out_msg.MessageSize := MessageSizeType:Response_Control;
}
}
out_msg.MessageSize := MessageSizeType:Response_Control;
}
}
@@
-444,7
+449,7
@@
machine(L2Cache, "MESI Directory L2 Cache CMP")
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:MEMORY_DATA;
out_msg.Sender := machineID;
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:MEMORY_DATA;
out_msg.Sender := machineID;
- out_msg.Destination.add(map
_Address_to_Directory(address
));
+ out_msg.Destination.add(map
AddressToMachine(address, MachineType:Directory
));
out_msg.DataBlk := tbe.DataBlk;
out_msg.Dirty := tbe.Dirty;
out_msg.MessageSize := MessageSizeType:Response_Data;
out_msg.DataBlk := tbe.DataBlk;
out_msg.Dirty := tbe.Dirty;
out_msg.MessageSize := MessageSizeType:Response_Data;
@@
-542,7
+547,7
@@
machine(L2Cache, "MESI Directory L2 Cache CMP")
out_msg.Destination.add(tbe.L1_GetX_ID);
DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
out_msg.DataBlk := cache_entry.DataBlk;
out_msg.Destination.add(tbe.L1_GetX_ID);
DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
out_msg.DataBlk := cache_entry.DataBlk;
- DPRINTF(RubySlicc, "Address: %
s
, Destination: %s, DataBlock: %s\n",
+ DPRINTF(RubySlicc, "Address: %
#x
, Destination: %s, DataBlock: %s\n",
out_msg.addr, out_msg.Destination, out_msg.DataBlk);
out_msg.MessageSize := MessageSizeType:Response_Data;
}
out_msg.addr, out_msg.Destination, out_msg.DataBlk);
out_msg.MessageSize := MessageSizeType:Response_Data;
}
@@
-604,15
+609,18
@@
machine(L2Cache, "MESI Directory L2 Cache CMP")
}
action(jj_popL1RequestQueue, "\j", desc="Pop incoming L1 request queue") {
}
action(jj_popL1RequestQueue, "\j", desc="Pop incoming L1 request queue") {
- profileMsgDelay(0, L1RequestL2Network_in.dequeue());
+ Tick delay := L1RequestL2Network_in.dequeue(clockEdge());
+ profileMsgDelay(0, ticksToCycles(delay));
}
action(k_popUnblockQueue, "k", desc="Pop incoming unblock queue") {
}
action(k_popUnblockQueue, "k", desc="Pop incoming unblock queue") {
- profileMsgDelay(0, L1unblockNetwork_in.dequeue());
+ Tick delay := L1unblockNetwork_in.dequeue(clockEdge());
+ profileMsgDelay(0, ticksToCycles(delay));
}
action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue") {
}
action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue") {
- profileMsgDelay(1, responseL2Network_in.dequeue());
+ Tick delay := responseL2Network_in.dequeue(clockEdge());
+ profileMsgDelay(1, ticksToCycles(delay));
}
action(m_writeDataToCache, "m", desc="Write data from response queue to cache") {
}
action(m_writeDataToCache, "m", desc="Write data from response queue to cache") {
@@
-769,7
+777,7
@@
machine(L2Cache, "MESI Directory L2 Cache CMP")
}
action(zn_recycleResponseNetwork, "zn", desc="recycle memory request") {
}
action(zn_recycleResponseNetwork, "zn", desc="recycle memory request") {
- responseL2Network_in.recycle();
+ responseL2Network_in.recycle(
clockEdge(), cyclesToTicks(recycle_latency)
);
}
action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
}
action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {