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i965/nir/vec4: Implement conditional statements (nir_cf_node_if)
[mesa.git]
/
src
/
mesa
/
drivers
/
dri
/
i965
/
brw_blorp.cpp
diff --git
a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 76537c8c2be814157f8107bee600d9a2227bc3eb..eac1f005496a3d83b3a67dd7b6b0ae8ddc334ddf 100644
(file)
--- a/
src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/
src/mesa/drivers/dri/i965/brw_blorp.cpp
@@
-68,8
+68,8
@@
brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
this->mt = mt;
this->level = level;
this->layer = layer;
this->mt = mt;
this->level = level;
this->layer = layer;
- this->width = m
t->level[level].width
;
- this->height = m
t->level[level].height
;
+ this->width = m
inify(mt->physical_width0, level - mt->first_level)
;
+ this->height = m
inify(mt->physical_height0, level - mt->first_level)
;
intel_miptree_get_image_offset(mt, level, layer, &x_offset, &y_offset);
}
intel_miptree_get_image_offset(mt, level, layer, &x_offset, &y_offset);
}
@@
-78,15
+78,18
@@
void
brw_blorp_surface_info::set(struct brw_context *brw,
struct intel_mipmap_tree *mt,
unsigned int level, unsigned int layer,
brw_blorp_surface_info::set(struct brw_context *brw,
struct intel_mipmap_tree *mt,
unsigned int level, unsigned int layer,
- bool is_render_target)
+
mesa_format format,
bool is_render_target)
{
brw_blorp_mip_info::set(mt, level, layer);
this->num_samples = mt->num_samples;
{
brw_blorp_mip_info::set(mt, level, layer);
this->num_samples = mt->num_samples;
- this->array_
spacing_lod0 = mt->array_spacing_lod0
;
+ this->array_
layout = mt->array_layout
;
this->map_stencil_as_y_tiled = false;
this->msaa_layout = mt->msaa_layout;
this->map_stencil_as_y_tiled = false;
this->msaa_layout = mt->msaa_layout;
- switch (mt->format) {
+ if (format == MESA_FORMAT_NONE)
+ format = mt->format;
+
+ switch (format) {
case MESA_FORMAT_S_UINT8:
/* The miptree is a W-tiled stencil buffer. Surface states can't be set
* up for W tiling, so we'll need to use Y tiling and have the WM
case MESA_FORMAT_S_UINT8:
/* The miptree is a W-tiled stencil buffer. Surface states can't be set
* up for W tiling, so we'll need to use Y tiling and have the WM
@@
-115,7
+118,7
@@
brw_blorp_surface_info::set(struct brw_context *brw,
this->brw_surfaceformat = BRW_SURFACEFORMAT_R16_UNORM;
break;
default: {
this->brw_surfaceformat = BRW_SURFACEFORMAT_R16_UNORM;
break;
default: {
- mesa_format linear_format = _mesa_get_srgb_format_linear(
mt->
format);
+ mesa_format linear_format = _mesa_get_srgb_format_linear(format);
if (is_render_target) {
assert(brw->format_supported_as_render_target[linear_format]);
this->brw_surfaceformat = brw->render_target_format[linear_format];
if (is_render_target) {
assert(brw->format_supported_as_render_target[linear_format]);
this->brw_surfaceformat = brw->render_target_format[linear_format];
@@
-139,35
+142,33
@@
uint32_t
brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
uint32_t *tile_y) const
{
brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
uint32_t *tile_y) const
{
- struct intel_region *region = mt->region;
uint32_t mask_x, mask_y;
uint32_t mask_x, mask_y;
- intel_region_get_tile_masks(region, &mask_x, &mask_y,
- map_stencil_as_y_tiled);
+ intel_miptree_get_tile_masks(mt, &mask_x, &mask_y, map_stencil_as_y_tiled);
*tile_x = x_offset & mask_x;
*tile_y = y_offset & mask_y;
*tile_x = x_offset & mask_x;
*tile_y = y_offset & mask_y;
- return intel_
region_get_aligned_offset(region
, x_offset & ~mask_x,
- y_offset & ~mask_y,
- map_stencil_as_y_tiled);
+ return intel_
miptree_get_aligned_offset(mt
, x_offset & ~mask_x,
+
y_offset & ~mask_y,
+
map_stencil_as_y_tiled);
}
}
-brw_blorp_params::brw_blorp_params()
+brw_blorp_params::brw_blorp_params(unsigned num_varyings,
+ unsigned num_draw_buffers,
+ unsigned num_layers)
: x0(0),
y0(0),
x1(0),
y1(0),
depth_format(0),
hiz_op(GEN6_HIZ_OP_NONE),
: x0(0),
y0(0),
x1(0),
y1(0),
depth_format(0),
hiz_op(GEN6_HIZ_OP_NONE),
- fast_clear_op(GEN7_FAST_CLEAR_OP_NONE),
- use_wm_prog(false)
+ use_wm_prog(false),
+ num_varyings(num_varyings),
+ num_draw_buffers(num_draw_buffers),
+ num_layers(num_layers)
{
{
- color_write_disable[0] = false;
- color_write_disable[1] = false;
- color_write_disable[2] = false;
- color_write_disable[3] = false;
}
extern "C" {
}
extern "C" {
@@
-193,10
+194,14
@@
intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
}
DBG("%s %s to mt %p level %d layer %d\n",
}
DBG("%s %s to mt %p level %d layer %d\n",
- __
FUNCTION
__, opname, mt, level, layer);
+ __
func
__, opname, mt, level, layer);
- brw_hiz_op_params params(mt, level, layer, op);
- brw_blorp_exec(brw, ¶ms);
+ if (brw->gen >= 8) {
+ gen8_hiz_exec(brw, mt, level, layer, op);
+ } else {
+ brw_hiz_op_params params(mt, level, layer, op);
+ brw_blorp_exec(brw, ¶ms);
+ }
}
} /* extern "C" */
}
} /* extern "C" */
@@
-215,13
+220,13
@@
brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params)
* data with different formats, which blorp does for stencil and depth
* data.
*/
* data with different formats, which blorp does for stencil and depth
* data.
*/
-
intel_batchbuffer
_emit_mi_flush(brw);
+
brw
_emit_mi_flush(brw);
retry:
intel_batchbuffer_require_space(brw, estimated_max_batch_usage, RENDER_RING);
intel_batchbuffer_save_state(brw);
drm_intel_bo *saved_bo = brw->batch.bo;
retry:
intel_batchbuffer_require_space(brw, estimated_max_batch_usage, RENDER_RING);
intel_batchbuffer_save_state(brw);
drm_intel_bo *saved_bo = brw->batch.bo;
- uint32_t saved_used =
brw->batch.used
;
+ uint32_t saved_used =
USED_BATCH(brw->batch)
;
uint32_t saved_state_batch_offset = brw->batch.state_batch_offset;
switch (brw->gen) {
uint32_t saved_state_batch_offset = brw->batch.state_batch_offset;
switch (brw->gen) {
@@
-233,15
+238,14
@@
retry:
break;
default:
/* BLORP is not supported before Gen6. */
break;
default:
/* BLORP is not supported before Gen6. */
- assert(false);
- break;
+ unreachable("not reached");
}
/* Make sure we didn't wrap the batch unintentionally, and make sure we
* reserved enough space that a wrap will never happen.
*/
assert(brw->batch.bo == saved_bo);
}
/* Make sure we didn't wrap the batch unintentionally, and make sure we
* reserved enough space that a wrap will never happen.
*/
assert(brw->batch.bo == saved_bo);
- assert((
brw->batch.used
- saved_used) * 4 +
+ assert((
USED_BATCH(brw->batch)
- saved_used) * 4 +
(saved_state_batch_offset - brw->batch.state_batch_offset) <
estimated_max_batch_usage);
/* Shut up compiler warnings on release build */
(saved_state_batch_offset - brw->batch.state_batch_offset) <
estimated_max_batch_usage);
/* Shut up compiler warnings on release build */
@@
-272,15
+276,14
@@
retry:
/* We've smashed all state compared to what the normal 3D pipeline
* rendering tracks for GL.
*/
/* We've smashed all state compared to what the normal 3D pipeline
* rendering tracks for GL.
*/
- brw->
state.dirty.brw = ~0
;
- brw->
state.dirty.cache = ~0
;
+ brw->
ctx.NewDriverState = ~0ull
;
+ brw->
no_depth_or_stencil = false
;
brw->ib.type = -1;
brw->ib.type = -1;
- intel_batchbuffer_clear_cache(brw);
/* Flush the sampler cache so any texturing from the destination is
* coherent.
*/
/* Flush the sampler cache so any texturing from the destination is
* coherent.
*/
-
intel_batchbuffer
_emit_mi_flush(brw);
+
brw
_emit_mi_flush(brw);
}
brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
}
brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
@@
-323,13
+326,13
@@
brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
x1 = depth.width;
y1 = depth.height;
x1 = depth.width;
y1 = depth.height;
- assert(intel_miptree_
slice_has_hiz(mt, level, layer
));
+ assert(intel_miptree_
level_has_hiz(mt, level
));
switch (mt->format) {
case MESA_FORMAT_Z_UNORM16: depth_format = BRW_DEPTHFORMAT_D16_UNORM; break;
case MESA_FORMAT_Z_FLOAT32: depth_format = BRW_DEPTHFORMAT_D32_FLOAT; break;
case MESA_FORMAT_Z24_UNORM_X8_UINT: depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; break;
switch (mt->format) {
case MESA_FORMAT_Z_UNORM16: depth_format = BRW_DEPTHFORMAT_D16_UNORM; break;
case MESA_FORMAT_Z_FLOAT32: depth_format = BRW_DEPTHFORMAT_D32_FLOAT; break;
case MESA_FORMAT_Z24_UNORM_X8_UINT: depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; break;
- default:
assert(0); break
;
+ default:
unreachable("not reached")
;
}
}
}
}