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i965/nir/vec4: Implement conditional statements (nir_cf_node_if)
[mesa.git]
/
src
/
mesa
/
drivers
/
dri
/
i965
/
brw_blorp.cpp
diff --git
a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index b57721ca005baf91841f20105cccc6c045fd373b..eac1f005496a3d83b3a67dd7b6b0ae8ddc334ddf 100644
(file)
--- a/
src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/
src/mesa/drivers/dri/i965/brw_blorp.cpp
@@
-78,15
+78,18
@@
void
brw_blorp_surface_info::set(struct brw_context *brw,
struct intel_mipmap_tree *mt,
unsigned int level, unsigned int layer,
brw_blorp_surface_info::set(struct brw_context *brw,
struct intel_mipmap_tree *mt,
unsigned int level, unsigned int layer,
- bool is_render_target)
+
mesa_format format,
bool is_render_target)
{
brw_blorp_mip_info::set(mt, level, layer);
this->num_samples = mt->num_samples;
{
brw_blorp_mip_info::set(mt, level, layer);
this->num_samples = mt->num_samples;
- this->array_
spacing_lod0 = mt->array_spacing_lod0
;
+ this->array_
layout = mt->array_layout
;
this->map_stencil_as_y_tiled = false;
this->msaa_layout = mt->msaa_layout;
this->map_stencil_as_y_tiled = false;
this->msaa_layout = mt->msaa_layout;
- switch (mt->format) {
+ if (format == MESA_FORMAT_NONE)
+ format = mt->format;
+
+ switch (format) {
case MESA_FORMAT_S_UINT8:
/* The miptree is a W-tiled stencil buffer. Surface states can't be set
* up for W tiling, so we'll need to use Y tiling and have the WM
case MESA_FORMAT_S_UINT8:
/* The miptree is a W-tiled stencil buffer. Surface states can't be set
* up for W tiling, so we'll need to use Y tiling and have the WM
@@
-115,7
+118,7
@@
brw_blorp_surface_info::set(struct brw_context *brw,
this->brw_surfaceformat = BRW_SURFACEFORMAT_R16_UNORM;
break;
default: {
this->brw_surfaceformat = BRW_SURFACEFORMAT_R16_UNORM;
break;
default: {
- mesa_format linear_format = _mesa_get_srgb_format_linear(
mt->
format);
+ mesa_format linear_format = _mesa_get_srgb_format_linear(format);
if (is_render_target) {
assert(brw->format_supported_as_render_target[linear_format]);
this->brw_surfaceformat = brw->render_target_format[linear_format];
if (is_render_target) {
assert(brw->format_supported_as_render_target[linear_format]);
this->brw_surfaceformat = brw->render_target_format[linear_format];
@@
-152,20
+155,20
@@
brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
}
}
-brw_blorp_params::brw_blorp_params()
+brw_blorp_params::brw_blorp_params(unsigned num_varyings,
+ unsigned num_draw_buffers,
+ unsigned num_layers)
: x0(0),
y0(0),
x1(0),
y1(0),
depth_format(0),
hiz_op(GEN6_HIZ_OP_NONE),
: x0(0),
y0(0),
x1(0),
y1(0),
depth_format(0),
hiz_op(GEN6_HIZ_OP_NONE),
- fast_clear_op(GEN7_FAST_CLEAR_OP_NONE),
- use_wm_prog(false)
+ use_wm_prog(false),
+ num_varyings(num_varyings),
+ num_draw_buffers(num_draw_buffers),
+ num_layers(num_layers)
{
{
- color_write_disable[0] = false;
- color_write_disable[1] = false;
- color_write_disable[2] = false;
- color_write_disable[3] = false;
}
extern "C" {
}
extern "C" {
@@
-191,7
+194,7
@@
intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
}
DBG("%s %s to mt %p level %d layer %d\n",
}
DBG("%s %s to mt %p level %d layer %d\n",
- __
FUNCTION
__, opname, mt, level, layer);
+ __
func
__, opname, mt, level, layer);
if (brw->gen >= 8) {
gen8_hiz_exec(brw, mt, level, layer, op);
if (brw->gen >= 8) {
gen8_hiz_exec(brw, mt, level, layer, op);
@@
-217,13
+220,13
@@
brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params)
* data with different formats, which blorp does for stencil and depth
* data.
*/
* data with different formats, which blorp does for stencil and depth
* data.
*/
-
intel_batchbuffer
_emit_mi_flush(brw);
+
brw
_emit_mi_flush(brw);
retry:
intel_batchbuffer_require_space(brw, estimated_max_batch_usage, RENDER_RING);
intel_batchbuffer_save_state(brw);
drm_intel_bo *saved_bo = brw->batch.bo;
retry:
intel_batchbuffer_require_space(brw, estimated_max_batch_usage, RENDER_RING);
intel_batchbuffer_save_state(brw);
drm_intel_bo *saved_bo = brw->batch.bo;
- uint32_t saved_used =
brw->batch.used
;
+ uint32_t saved_used =
USED_BATCH(brw->batch)
;
uint32_t saved_state_batch_offset = brw->batch.state_batch_offset;
switch (brw->gen) {
uint32_t saved_state_batch_offset = brw->batch.state_batch_offset;
switch (brw->gen) {
@@
-242,7
+245,7
@@
retry:
* reserved enough space that a wrap will never happen.
*/
assert(brw->batch.bo == saved_bo);
* reserved enough space that a wrap will never happen.
*/
assert(brw->batch.bo == saved_bo);
- assert((
brw->batch.used
- saved_used) * 4 +
+ assert((
USED_BATCH(brw->batch)
- saved_used) * 4 +
(saved_state_batch_offset - brw->batch.state_batch_offset) <
estimated_max_batch_usage);
/* Shut up compiler warnings on release build */
(saved_state_batch_offset - brw->batch.state_batch_offset) <
estimated_max_batch_usage);
/* Shut up compiler warnings on release build */
@@
-273,15
+276,14
@@
retry:
/* We've smashed all state compared to what the normal 3D pipeline
* rendering tracks for GL.
*/
/* We've smashed all state compared to what the normal 3D pipeline
* rendering tracks for GL.
*/
- brw->state.dirty.brw = ~0;
- brw->state.dirty.cache = ~0;
+ brw->ctx.NewDriverState = ~0ull;
brw->no_depth_or_stencil = false;
brw->ib.type = -1;
/* Flush the sampler cache so any texturing from the destination is
* coherent.
*/
brw->no_depth_or_stencil = false;
brw->ib.type = -1;
/* Flush the sampler cache so any texturing from the destination is
* coherent.
*/
-
intel_batchbuffer
_emit_mi_flush(brw);
+
brw
_emit_mi_flush(brw);
}
brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
}
brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,