+struct intel_sync_object {
+ struct gl_sync_object Base;
+
+ /** Batch associated with this sync object */
+ drm_intel_bo *bo;
+};
+
+struct intel_batchbuffer {
+ /** Current batchbuffer being queued up. */
+ drm_intel_bo *bo;
+ /** Last BO submitted to the hardware. Used for glFinish(). */
+ drm_intel_bo *last_bo;
+ /** BO for post-sync nonzero writes for gen6 workaround. */
+ drm_intel_bo *workaround_bo;
+ bool need_workaround_flush;
+
+ struct cached_batch_item *cached_items;
+
+ uint16_t emit, total;
+ uint16_t used, reserved_space;
+ uint32_t *map;
+ uint32_t *cpu_map;
+#define BATCH_SZ (8192*sizeof(uint32_t))
+
+ uint32_t state_batch_offset;
+ bool is_blit;
+ bool needs_sol_reset;
+
+ struct {
+ uint16_t used;
+ int reloc_count;
+ } saved;
+};
+
+#define BRW_MAX_XFB_STREAMS 4
+
+struct brw_transform_feedback_object {
+ struct gl_transform_feedback_object base;
+
+ /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
+ drm_intel_bo *offset_bo;
+
+ /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
+ GLenum primitive_mode;
+
+ /**
+ * Count of primitives generated during this transform feedback operation.
+ * @{
+ */
+ uint64_t prims_generated[BRW_MAX_XFB_STREAMS];
+ drm_intel_bo *prim_count_bo;
+ unsigned prim_count_buffer_index; /**< in number of uint64_t units */
+ /** @} */
+
+ /**
+ * Number of vertices written between last Begin/EndTransformFeedback().
+ *
+ * Used to implement DrawTransformFeedback().
+ */
+ uint64_t vertices_written[BRW_MAX_XFB_STREAMS];
+ bool vertices_written_valid;
+};
+
+/**
+ * Data shared between each programmable stage in the pipeline (vs, gs, and
+ * wm).
+ */
+struct brw_stage_state
+{
+ struct brw_stage_prog_data *prog_data;
+
+ /**
+ * Optional scratch buffer used to store spilled register values and
+ * variably-indexed GRF arrays.
+ */
+ drm_intel_bo *scratch_bo;
+
+ /** Pull constant buffer */
+ drm_intel_bo *const_bo;
+
+ /** Offset in the program cache to the program */
+ uint32_t prog_offset;
+
+ /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
+ uint32_t state_offset;
+
+ uint32_t push_const_offset; /* Offset in the batchbuffer */
+ int push_const_size; /* in 256-bit register increments */
+
+ /* Binding table: pointers to SURFACE_STATE entries. */
+ uint32_t bind_bo_offset;
+ uint32_t surf_offset[BRW_MAX_SURFACES];
+
+ /** SAMPLER_STATE count and table offset */
+ uint32_t sampler_count;
+ uint32_t sampler_offset;
+
+ /** Offsets in the batch to sampler default colors (texture border color) */
+ uint32_t sdc_offset[BRW_MAX_TEX_UNIT];
+};
+