- }
-
- if (uses_draw_params) {
- EMIT_VERTEX_BUFFER_STATE(brw, brw->vb.nr_buffers,
- brw->draw.draw_params_bo,
- brw->draw.draw_params_bo->size - 1,
- brw->draw.draw_params_offset,
- 0, /* stride */
- 0); /* step rate */
- }
-
- if (brw->vs.prog_data->uses_drawid) {
- EMIT_VERTEX_BUFFER_STATE(brw, brw->vb.nr_buffers + 1,
- brw->draw.draw_id_bo,
- brw->draw.draw_id_bo->size - 1,
- brw->draw.draw_id_offset,
- 0, /* stride */
- 0); /* step rate */
- }
-
- ADVANCE_BATCH();
- }
-
- /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS, presumably
- * for VertexID/InstanceID.
- */
- if (brw->gen >= 6) {
- assert(nr_elements <= 34);
- } else {
- assert(nr_elements <= 18);
- }
-
- struct brw_vertex_element *gen6_edgeflag_input = NULL;
-
- BEGIN_BATCH(1 + nr_elements * 2);
- OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (2 * nr_elements - 1));
- for (i = 0; i < brw->vb.nr_enabled; i++) {
- struct brw_vertex_element *input = brw->vb.enabled[i];
- uint32_t format = brw_get_vertex_surface_type(brw, input->glarray);
- uint32_t comp0 = BRW_VE1_COMPONENT_STORE_SRC;
- uint32_t comp1 = BRW_VE1_COMPONENT_STORE_SRC;
- uint32_t comp2 = BRW_VE1_COMPONENT_STORE_SRC;
- uint32_t comp3 = BRW_VE1_COMPONENT_STORE_SRC;
-
- if (input == &brw->vb.inputs[VERT_ATTRIB_EDGEFLAG]) {
- /* Gen6+ passes edgeflag as sideband along with the vertex, instead
- * of in the VUE. We have to upload it sideband as the last vertex
- * element according to the B-Spec.
- */
- if (brw->gen >= 6) {
- gen6_edgeflag_input = input;
- continue;
- }
- }
-
- switch (input->glarray->Size) {
- case 0: comp0 = BRW_VE1_COMPONENT_STORE_0;
- case 1: comp1 = BRW_VE1_COMPONENT_STORE_0;
- case 2: comp2 = BRW_VE1_COMPONENT_STORE_0;
- case 3: comp3 = input->glarray->Integer ? BRW_VE1_COMPONENT_STORE_1_INT
- : BRW_VE1_COMPONENT_STORE_1_FLT;
- break;
- }
-
- if (brw->gen >= 6) {
- OUT_BATCH((input->buffer << GEN6_VE0_INDEX_SHIFT) |
- GEN6_VE0_VALID |
- (format << BRW_VE0_FORMAT_SHIFT) |
- (input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
- } else {
- OUT_BATCH((input->buffer << BRW_VE0_INDEX_SHIFT) |
- BRW_VE0_VALID |
- (format << BRW_VE0_FORMAT_SHIFT) |
- (input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
- }
-
- if (brw->gen >= 5)
- OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
- (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
- (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
- (comp3 << BRW_VE1_COMPONENT_3_SHIFT));
- else
- OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
- (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
- (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
- (comp3 << BRW_VE1_COMPONENT_3_SHIFT) |
- ((i * 4) << BRW_VE1_DST_OFFSET_SHIFT));
- }
-
- if (brw->vs.prog_data->uses_vertexid || brw->vs.prog_data->uses_instanceid ||
- brw->vs.prog_data->uses_basevertex || brw->vs.prog_data->uses_baseinstance) {
- uint32_t dw0 = 0, dw1 = 0;
- uint32_t comp0 = BRW_VE1_COMPONENT_STORE_0;
- uint32_t comp1 = BRW_VE1_COMPONENT_STORE_0;
- uint32_t comp2 = BRW_VE1_COMPONENT_STORE_0;
- uint32_t comp3 = BRW_VE1_COMPONENT_STORE_0;
-
- if (brw->vs.prog_data->uses_basevertex)
- comp0 = BRW_VE1_COMPONENT_STORE_SRC;
-
- if (brw->vs.prog_data->uses_baseinstance)
- comp1 = BRW_VE1_COMPONENT_STORE_SRC;
-
- if (brw->vs.prog_data->uses_vertexid)
- comp2 = BRW_VE1_COMPONENT_STORE_VID;
-
- if (brw->vs.prog_data->uses_instanceid)
- comp3 = BRW_VE1_COMPONENT_STORE_IID;
-
- dw1 = (comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
- (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
- (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
- (comp3 << BRW_VE1_COMPONENT_3_SHIFT);
-
- if (brw->gen >= 6) {
- dw0 |= GEN6_VE0_VALID |
- brw->vb.nr_buffers << GEN6_VE0_INDEX_SHIFT |
- BRW_SURFACEFORMAT_R32G32_UINT << BRW_VE0_FORMAT_SHIFT;
- } else {
- dw0 |= BRW_VE0_VALID |
- brw->vb.nr_buffers << BRW_VE0_INDEX_SHIFT |
- BRW_SURFACEFORMAT_R32G32_UINT << BRW_VE0_FORMAT_SHIFT;
- dw1 |= (i * 4) << BRW_VE1_DST_OFFSET_SHIFT;
- }
-
- /* Note that for gl_VertexID, gl_InstanceID, and gl_PrimitiveID values,
- * the format is ignored and the value is always int.
- */
-
- OUT_BATCH(dw0);
- OUT_BATCH(dw1);
- }
-
- if (brw->vs.prog_data->uses_drawid) {
- uint32_t dw0 = 0, dw1 = 0;
-
- dw1 = (BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT) |
- (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
- (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
- (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT);
-
- if (brw->gen >= 6) {
- dw0 |= GEN6_VE0_VALID |
- ((brw->vb.nr_buffers + 1) << GEN6_VE0_INDEX_SHIFT) |
- (BRW_SURFACEFORMAT_R32_UINT << BRW_VE0_FORMAT_SHIFT);
- } else {
- dw0 |= BRW_VE0_VALID |
- ((brw->vb.nr_buffers + 1) << BRW_VE0_INDEX_SHIFT) |
- (BRW_SURFACEFORMAT_R32_UINT << BRW_VE0_FORMAT_SHIFT);
-
- dw1 |= (i * 4) << BRW_VE1_DST_OFFSET_SHIFT;
- }
-
- OUT_BATCH(dw0);
- OUT_BATCH(dw1);