- brw_alloc_reg_set_for_classes(brw, class_sizes, class_count,
- reg_width, base_reg_count);
-
- struct ra_graph *g = ra_alloc_interference_graph(brw->wm.regs,
- this->virtual_grf_next);
-
- for (int i = 0; i < this->virtual_grf_next; i++) {
- for (int c = 0; c < class_count; c++) {
- if (class_sizes[c] == this->virtual_grf_sizes[i]) {
- if (brw->wm.aligned_pairs_class >= 0 &&
- this->delta_x.reg == i) {
- ra_set_node_class(g, i, brw->wm.aligned_pairs_class);
- } else {
- ra_set_node_class(g, i, brw->wm.classes[c]);
- }
- break;
- }
+/**
+ * Sets interference between virtual GRFs and usage of the high GRFs for SEND
+ * messages (treated as MRFs in code generation).
+ */
+void
+fs_visitor::setup_mrf_hack_interference(struct ra_graph *g, int first_mrf_node)
+{
+ int reg_width = dispatch_width / 8;
+
+ bool mrf_used[BRW_MAX_MRF];
+ get_used_mrfs(mrf_used);
+
+ for (int i = 0; i < BRW_MAX_MRF; i++) {
+ /* Mark each MRF reg node as being allocated to its physical register.
+ *
+ * The alternative would be to have per-physical-register classes, which
+ * would just be silly.
+ */
+ ra_set_node_reg(g, first_mrf_node + i,
+ (GEN7_MRF_HACK_START + i) / reg_width);
+
+ /* Since we don't have any live/dead analysis on the MRFs, just mark all
+ * that are used as conflicting with all virtual GRFs.
+ */
+ if (mrf_used[i]) {
+ for (int j = 0; j < this->virtual_grf_count; j++) {
+ ra_add_node_interference(g, first_mrf_node + i, j);
+ }
+ }
+ }
+}
+
+bool
+fs_visitor::assign_regs(bool allow_spilling)
+{
+ struct intel_screen *screen = brw->intelScreen;
+ /* Most of this allocation was written for a reg_width of 1
+ * (dispatch_width == 8). In extending to SIMD16, the code was
+ * left in place and it was converted to have the hardware
+ * registers it's allocating be contiguous physical pairs of regs
+ * for reg_width == 2.
+ */
+ int reg_width = dispatch_width / 8;
+ int hw_reg_mapping[this->virtual_grf_count];
+ int payload_node_count = (ALIGN(this->first_non_payload_grf, reg_width) /
+ reg_width);
+ int rsi = reg_width - 1; /* Which screen->wm_reg_sets[] to use */
+ calculate_live_intervals();
+
+ int node_count = this->virtual_grf_count;
+ int first_payload_node = node_count;
+ node_count += payload_node_count;
+ int first_mrf_hack_node = node_count;
+ if (brw->gen >= 7)
+ node_count += BRW_MAX_GRF - GEN7_MRF_HACK_START;
+ struct ra_graph *g = ra_alloc_interference_graph(screen->wm_reg_sets[rsi].regs,
+ node_count);
+
+ for (int i = 0; i < this->virtual_grf_count; i++) {
+ unsigned size = this->virtual_grf_sizes[i];
+ int c;
+
+ assert(size <= ARRAY_SIZE(screen->wm_reg_sets[rsi].classes) &&
+ "Register allocation relies on split_virtual_grfs()");
+ c = screen->wm_reg_sets[rsi].classes[size - 1];
+
+ /* Special case: on pre-GEN6 hardware that supports PLN, the
+ * second operand of a PLN instruction needs to be an
+ * even-numbered register, so we have a special register class
+ * wm_aligned_pairs_class to handle this case. pre-GEN6 always
+ * uses this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] as the
+ * second operand of a PLN instruction (since it doesn't support
+ * any other interpolation modes). So all we need to do is find
+ * that register and set it to the appropriate class.
+ */
+ if (screen->wm_reg_sets[rsi].aligned_pairs_class >= 0 &&
+ this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].file == GRF &&
+ this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].reg == i) {
+ c = screen->wm_reg_sets[rsi].aligned_pairs_class;