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i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush.
[mesa.git]
/
src
/
mesa
/
drivers
/
dri
/
i965
/
brw_misc_state.c
diff --git
a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 690c2f65fd946c6ff8e860cf28cecc2ca01e668f..c3d341fd1116dbd04267757715b0d70365b02618 100644
(file)
--- a/
src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/
src/mesa/drivers/dri/i965/brw_misc_state.c
@@
-925,15
+925,6
@@
brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline)
const unsigned dc_flush =
brw->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
const unsigned dc_flush =
brw->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
- if (brw->gen == 6) {
- /* Hardware workaround: SNB B-Spec says:
- *
- * Before a PIPE_CONTROL with Write Cache Flush Enable = 1, a
- * PIPE_CONTROL with any non-zero post-sync-op is required.
- */
- brw_emit_post_sync_nonzero_flush(brw);
- }
-
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |