+ enum register_file file; /**< Register file: GRF, MRF, IMM. */
+ enum brw_reg_type type; /**< Register type: BRW_REGISTER_TYPE_* */
+
+ /**
+ * Register number.
+ *
+ * For GRF, it's a virtual register number until register allocation.
+ *
+ * For MRF, it's the hardware register.
+ */
+ uint16_t reg;
+
+ /**
+ * Offset within the virtual register.
+ *
+ * In the scalar backend, this is in units of a float per pixel for pre-
+ * register allocation registers (i.e., one register in SIMD8 mode and two
+ * registers in SIMD16 mode).
+ *
+ * For uniforms, this is in units of 1 float.
+ */
+ int reg_offset;
+
+ struct brw_reg fixed_hw_reg;
+
+ bool negate;
+ bool abs;
+};
+
+struct cfg_t;
+struct bblock_t;
+
+#ifdef __cplusplus
+struct backend_instruction : public exec_node {
+ bool is_3src() const;
+ bool is_tex() const;
+ bool is_math() const;
+ bool is_control_flow() const;
+ bool can_do_source_mods() const;
+ bool can_do_saturate() const;
+ bool can_do_cmod() const;
+ bool reads_accumulator_implicitly() const;
+ bool writes_accumulator_implicitly(struct brw_context *brw) const;
+
+ void remove(bblock_t *block);
+ void insert_after(bblock_t *block, backend_instruction *inst);
+ void insert_before(bblock_t *block, backend_instruction *inst);
+ void insert_before(bblock_t *block, exec_list *list);