+#define MAX_SAMPLER_MESSAGE_SIZE 11
+#define MAX_VGRF_SIZE 16
+
+struct brw_compiler {
+ const struct brw_device_info *devinfo;
+
+ struct {
+ struct ra_regs *regs;
+
+ /**
+ * Array of the ra classes for the unaligned contiguous register
+ * block sizes used.
+ */
+ int *classes;
+
+ /**
+ * Mapping for register-allocated objects in *regs to the first
+ * GRF for that object.
+ */
+ uint8_t *ra_reg_to_grf;
+ } vec4_reg_set;
+
+ struct {
+ struct ra_regs *regs;
+
+ /**
+ * Array of the ra classes for the unaligned contiguous register
+ * block sizes used, indexed by register size.
+ */
+ int classes[16];
+
+ /**
+ * Mapping from classes to ra_reg ranges. Each of the per-size
+ * classes corresponds to a range of ra_reg nodes. This array stores
+ * those ranges in the form of first ra_reg in each class and the
+ * total number of ra_reg elements in the last array element. This
+ * way the range of the i'th class is given by:
+ * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
+ */
+ int class_to_ra_reg_range[17];
+
+ /**
+ * Mapping for register-allocated objects in *regs to the first
+ * GRF for that object.
+ */
+ uint8_t *ra_reg_to_grf;
+
+ /**
+ * ra class for the aligned pairs we use for PLN, which doesn't
+ * appear in *classes.
+ */
+ int aligned_pairs_class;
+ } fs_reg_sets[2];
+
+ void (*shader_debug_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
+ void (*shader_perf_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
+
+ bool scalar_vs;
+ struct gl_shader_compiler_options glsl_compiler_options[MESA_SHADER_STAGES];
+};
+
+enum PACKED register_file {
+ BAD_FILE,
+ GRF,
+ MRF,
+ IMM,
+ HW_REG, /* a struct brw_reg */
+ ATTR,
+ UNIFORM, /* prog_data->params[reg] */
+};
+
+struct backend_reg
+{
+#ifdef __cplusplus
+ bool is_zero() const;
+ bool is_one() const;
+ bool is_negative_one() const;
+ bool is_null() const;
+ bool is_accumulator() const;
+ bool in_range(const backend_reg &r, unsigned n) const;
+#endif
+
+ enum register_file file; /**< Register file: GRF, MRF, IMM. */
+ enum brw_reg_type type; /**< Register type: BRW_REGISTER_TYPE_* */
+
+ /**
+ * Register number.
+ *
+ * For GRF, it's a virtual register number until register allocation.
+ *
+ * For MRF, it's the hardware register.
+ */
+ uint16_t reg;
+
+ /**
+ * Offset within the virtual register.
+ *
+ * In the scalar backend, this is in units of a float per pixel for pre-
+ * register allocation registers (i.e., one register in SIMD8 mode and two
+ * registers in SIMD16 mode).
+ *
+ * For uniforms, this is in units of 1 float.
+ */
+ uint16_t reg_offset;
+
+ struct brw_reg fixed_hw_reg;
+
+ bool negate;
+ bool abs;
+};
+
+struct cfg_t;
+struct bblock_t;
+
+#ifdef __cplusplus
+struct backend_instruction : public exec_node {
+ bool is_3src() const;
+ bool is_tex() const;
+ bool is_math() const;
+ bool is_control_flow() const;
+ bool is_commutative() const;
+ bool can_do_source_mods() const;
+ bool can_do_saturate() const;
+ bool can_do_cmod() const;
+ bool reads_accumulator_implicitly() const;
+ bool writes_accumulator_implicitly(const struct brw_device_info *devinfo) const;
+
+ void remove(bblock_t *block);
+ void insert_after(bblock_t *block, backend_instruction *inst);
+ void insert_before(bblock_t *block, backend_instruction *inst);
+ void insert_before(bblock_t *block, exec_list *list);
+
+ /**
+ * True if the instruction has side effects other than writing to
+ * its destination registers. You are expected not to reorder or
+ * optimize these out unless you know what you are doing.
+ */
+ bool has_side_effects() const;
+#else
+struct backend_instruction {
+ struct exec_node link;
+#endif
+ /** @{
+ * Annotation for the generated IR. One of the two can be set.
+ */
+ const void *ir;
+ const char *annotation;
+ /** @} */
+
+ uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
+ uint8_t mlen; /**< SEND message length */
+ int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
+ uint8_t target; /**< MRT target. */
+ uint8_t regs_written; /**< Number of registers written by the instruction. */
+