-
-static void
-gen7_update_buffer_texture_surface(struct gl_context *ctx,
- unsigned unit,
- uint32_t *binding_table,
- unsigned surf_index)
-{
- struct brw_context *brw = brw_context(ctx);
- struct intel_context *intel = &brw->intel;
- struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
- struct intel_buffer_object *intel_obj =
- intel_buffer_object(tObj->BufferObject);
- drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;
- gl_format format = tObj->_BufferObjectFormat;
-
- uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 8 * 4, 32, &binding_table[surf_index]);
- memset(surf, 0, 8 * 4);
-
- uint32_t surface_format = brw_format_for_mesa_format(format);
- if (surface_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
- _mesa_problem(NULL, "bad format %s for texture buffer\n",
- _mesa_get_format_name(format));
- }
-
- surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
- surface_format << BRW_SURFACE_FORMAT_SHIFT |
- BRW_SURFACE_RC_READ_WRITE;
-
- if (bo) {
- surf[1] = bo->offset; /* reloc */
-
- /* Emit relocation to surface contents. Section 5.1.1 of the gen4
- * bspec ("Data Cache") says that the data cache does not exist as
- * a separate cache and is just the sampler cache.
- */
- drm_intel_bo_emit_reloc(intel->batch.bo,
- binding_table[surf_index] + 4,
- bo, 0,
- I915_GEM_DOMAIN_SAMPLER, 0);
-
- int texel_size = _mesa_get_format_bytes(format);
- int w = intel_obj->Base.Size / texel_size;
- surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) | /* bits 6:0 of size */
- SET_FIELD((w >> 7) & 0x1fff, GEN7_SURFACE_HEIGHT); /* 19:7 */
- surf[3] = SET_FIELD((w >> 20) & 0x7f, BRW_SURFACE_DEPTH) | /* bits 26:20 */
- (texel_size - 1);
- }
-
- gen7_check_surface_setup(surf, false /* is_render_target */);
-}
-
-static void
-gen7_update_texture_surface(struct gl_context *ctx,
- unsigned unit,
- uint32_t *binding_table,
- unsigned surf_index)
-{
- struct brw_context *brw = brw_context(ctx);
- struct intel_context *intel = &brw->intel;
- struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
- struct intel_texture_object *intelObj = intel_texture_object(tObj);
- struct intel_mipmap_tree *mt = intelObj->mt;
- struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
- struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
- int width, height, depth;
- uint32_t tile_x, tile_y;
-
- if (tObj->Target == GL_TEXTURE_BUFFER) {
- gen7_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
- return;
- }
-
- intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
-
- uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 8 * 4, 32, &binding_table[surf_index]);
- memset(surf, 0, 8 * 4);
-
- uint32_t tex_format = translate_tex_format(intel,
- mt->format,
- firstImage->InternalFormat,
- tObj->DepthMode,
- sampler->sRGBDecode);
-
- surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
- tex_format << BRW_SURFACE_FORMAT_SHIFT |
- gen7_surface_tiling_mode(mt->region->tiling) |
- BRW_SURFACE_CUBEFACE_ENABLES;
-
- if (mt->align_h == 4)
- surf[0] |= GEN7_SURFACE_VALIGN_4;
- if (mt->align_w == 8)
- surf[0] |= GEN7_SURFACE_HALIGN_8;
-
- if (depth > 1 && tObj->Target != GL_TEXTURE_3D)
- surf[0] |= GEN7_SURFACE_IS_ARRAY;
-
- if (mt->array_spacing_lod0)
- surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
-
- surf[1] = mt->region->bo->offset + mt->offset; /* reloc */
-
- surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
- SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
- surf[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) |
- ((intelObj->mt->region->pitch) - 1);
-
- surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
-
- intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0,
- &tile_x, &tile_y);
- assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
- /* Note that the low bits of these fields are missing, so
- * there's the possibility of getting in trouble.
- */
- surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
- (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
- /* mip count */
- (intelObj->_MaxLevel - tObj->BaseLevel));
-
- if (intel->is_haswell) {
- /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
- * texturing functions that return a float, as our code generation always
- * selects the .x channel (which would always be 0).
- */
- const bool alpha_depth = tObj->DepthMode == GL_ALPHA &&
- (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
- firstImage->_BaseFormat == GL_DEPTH_STENCIL);
-
- const int swizzle = unlikely(alpha_depth)
- ? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj);
-
- surf[7] =
- SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0)), GEN7_SURFACE_SCS_R) |
- SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1)), GEN7_SURFACE_SCS_G) |
- SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2)), GEN7_SURFACE_SCS_B) |
- SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3)), GEN7_SURFACE_SCS_A);
- }
-
- /* Emit relocation to surface contents */
- drm_intel_bo_emit_reloc(brw->intel.batch.bo,
- binding_table[surf_index] + 4,
- intelObj->mt->region->bo, intelObj->mt->offset,
- I915_GEM_DOMAIN_SAMPLER, 0);
-
- gen7_check_surface_setup(surf, false /* is_render_target */);
-}
-
-/**
- * Create the constant buffer surface. Vertex/fragment shader constants will
- * be read from this buffer with Data Port Read instructions/messages.
- */
-static void
-gen7_create_constant_surface(struct brw_context *brw,
- drm_intel_bo *bo,
- uint32_t offset,
- uint32_t size,
- uint32_t *out_offset)
-{
- struct intel_context *intel = &brw->intel;
- uint32_t stride = 16;
- uint32_t elements = ALIGN(size, stride) / stride;
- const GLint w = elements - 1;
-
- uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 8 * 4, 32, out_offset);
- memset(surf, 0, 8 * 4);
-
- surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
- BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT |
- BRW_SURFACE_RC_READ_WRITE;
-
- assert(bo);
- surf[1] = bo->offset + offset; /* reloc */
-
- surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) |
- SET_FIELD((w >> 7) & 0x1fff, GEN7_SURFACE_HEIGHT);
- surf[3] = SET_FIELD((w >> 20) & 0x7f, BRW_SURFACE_DEPTH) |
- (stride - 1);
-
- if (intel->is_haswell) {
- surf[7] = SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
- SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
- SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) |
- SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
- }
-
- /* Emit relocation to surface contents. Section 5.1.1 of the gen4
- * bspec ("Data Cache") says that the data cache does not exist as
- * a separate cache and is just the sampler cache.
- */
- drm_intel_bo_emit_reloc(intel->batch.bo,
- *out_offset + 4,
- bo, offset,
- I915_GEM_DOMAIN_SAMPLER, 0);
-
- gen7_check_surface_setup(surf, false /* is_render_target */);
-}
-