-static void
-gen7_emit_buffer_surface_state(struct brw_context *brw,
- uint32_t *out_offset,
- drm_intel_bo *bo,
- unsigned buffer_offset,
- unsigned surface_format,
- unsigned buffer_size,
- unsigned pitch,
- bool rw)
-{
- uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 8 * 4, 32, out_offset);
- memset(surf, 0, 8 * 4);
-
- surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
- surface_format << BRW_SURFACE_FORMAT_SHIFT |
- BRW_SURFACE_RC_READ_WRITE;
- surf[1] = (bo ? bo->offset64 : 0) + buffer_offset; /* reloc */
- surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
- SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
- surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH) |
- (pitch - 1);
-
- surf[5] = SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS);
-
- if (brw->is_haswell) {
- surf[7] |= (SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
- SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
- SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) |
- SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
- }
-
- /* Emit relocation to surface contents */
- if (bo) {
- drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 4,
- bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
- (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
- }
-
- gen7_check_surface_setup(surf, false /* is_render_target */);
-}
-
-static void
-gen7_update_texture_surface(struct gl_context *ctx,
- unsigned unit,
- uint32_t *surf_offset,
- bool for_gather)
-{
- struct brw_context *brw = brw_context(ctx);
- struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
- struct intel_texture_object *intelObj = intel_texture_object(tObj);
- struct intel_mipmap_tree *mt = intelObj->mt;
- struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
- struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
-
- if (tObj->Target == GL_TEXTURE_BUFFER) {
- brw_update_buffer_texture_surface(ctx, unit, surf_offset);
- return;
- }
-
- uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 8 * 4, 32, surf_offset);
- memset(surf, 0, 8 * 4);
-
- uint32_t tex_format = translate_tex_format(brw,
- intelObj->_Format,
- sampler->sRGBDecode);
-
- if (for_gather && tex_format == BRW_SURFACEFORMAT_R32G32_FLOAT)
- tex_format = BRW_SURFACEFORMAT_R32G32_FLOAT_LD;
-
- surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
- tex_format << BRW_SURFACE_FORMAT_SHIFT |
- gen7_surface_tiling_mode(mt->tiling);
-
- /* mask of faces present in cube map; for other surfaces MBZ. */
- if (tObj->Target == GL_TEXTURE_CUBE_MAP || tObj->Target == GL_TEXTURE_CUBE_MAP_ARRAY)
- surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
-
- if (mt->align_h == 4)
- surf[0] |= GEN7_SURFACE_VALIGN_4;
- if (mt->align_w == 8)
- surf[0] |= GEN7_SURFACE_HALIGN_8;
-
- if (_mesa_is_array_texture(tObj->Target) ||
- tObj->Target == GL_TEXTURE_CUBE_MAP)
- surf[0] |= GEN7_SURFACE_IS_ARRAY;
-
- /* if this is a view with restricted NumLayers, then
- * our effective depth is not just the miptree depth.
- */
- uint32_t effective_depth = (tObj->Immutable && tObj->Target != GL_TEXTURE_3D)
- ? tObj->NumLayers : mt->logical_depth0;
-
- if (mt->array_layout == ALL_SLICES_AT_EACH_LOD)
- surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
-
- surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
-
- surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
- SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
-
- surf[3] = SET_FIELD(effective_depth - 1, BRW_SURFACE_DEPTH) |
- (mt->pitch - 1);
-
- if (brw->is_haswell && tObj->_IsIntegerFormat)
- surf[3] |= HSW_SURFACE_IS_INTEGER_FORMAT;
-
- surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
- SET_FIELD(tObj->MinLayer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
- SET_FIELD((effective_depth - 1),
- GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT);
-
- surf[5] = (SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) |
- SET_FIELD(tObj->MinLevel + tObj->BaseLevel - mt->first_level, GEN7_SURFACE_MIN_LOD) |
- /* mip count */
- (intelObj->_MaxLevel - tObj->BaseLevel));
-
- surf[7] = mt->fast_clear_color_value;
-
- if (brw->is_haswell) {
- /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
- * texturing functions that return a float, as our code generation always
- * selects the .x channel (which would always be 0).
- */
- const bool alpha_depth = tObj->DepthMode == GL_ALPHA &&
- (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
- firstImage->_BaseFormat == GL_DEPTH_STENCIL);
-
- const int swizzle = unlikely(alpha_depth)
- ? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj);
-
- const bool need_scs_green_to_blue = for_gather && tex_format == BRW_SURFACEFORMAT_R32G32_FLOAT_LD;
-
- surf[7] |=
- SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0), need_scs_green_to_blue), GEN7_SURFACE_SCS_R) |
- SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1), need_scs_green_to_blue), GEN7_SURFACE_SCS_G) |
- SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2), need_scs_green_to_blue), GEN7_SURFACE_SCS_B) |
- SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3), need_scs_green_to_blue), GEN7_SURFACE_SCS_A);
- }
-
- if (mt->mcs_mt) {
- gen7_set_surface_mcs_info(brw, surf, *surf_offset,
- mt->mcs_mt, false /* is RT */);
- }
-
- /* Emit relocation to surface contents */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- *surf_offset + 4,
- mt->bo,
- surf[1] - mt->bo->offset64,
- I915_GEM_DOMAIN_SAMPLER, 0);
-
- gen7_check_surface_setup(surf, false /* is_render_target */);
-}
-