- switch (tiling) {
- case I915_TILING_X:
- return GEN8_SURFACE_TILING_X;
- case I915_TILING_Y:
- return GEN8_SURFACE_TILING_Y;
- default:
- return GEN8_SURFACE_TILING_NONE;
- }
-}
-
-static unsigned
-vertical_alignment(struct intel_mipmap_tree *mt)
-{
- switch (mt->align_h) {
- case 4:
- return GEN8_SURFACE_VALIGN_4;
- case 8:
- return GEN8_SURFACE_VALIGN_8;
- case 16:
- return GEN8_SURFACE_VALIGN_16;
- default:
- assert(!"Unsupported vertical surface alignment.");
- return GEN8_SURFACE_VALIGN_4;
- }
-}
-
-static unsigned
-horizontal_alignment(struct intel_mipmap_tree *mt)
-{
- switch (mt->align_w) {
- case 4:
- return GEN8_SURFACE_HALIGN_4;
- case 8:
- return GEN8_SURFACE_HALIGN_8;
- case 16:
- return GEN8_SURFACE_HALIGN_16;
- default:
- assert(!"Unsupported horizontal surface alignment.");
- return GEN8_SURFACE_HALIGN_4;
- }
-}
-
-static void
-gen8_emit_buffer_surface_state(struct brw_context *brw,
- uint32_t *out_offset,
- drm_intel_bo *bo,
- unsigned buffer_offset,
- unsigned surface_format,
- unsigned buffer_size,
- unsigned pitch,
- unsigned mocs,
- bool rw)
-{
- uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 13 * 4, 64, out_offset);
- memset(surf, 0, 13 * 4);
-
- surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
- surface_format << BRW_SURFACE_FORMAT_SHIFT |
- BRW_SURFACE_RC_READ_WRITE;
-
- surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
- SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
- surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH) |
- (pitch - 1);
- surf[7] = SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
- SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
- SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) |
- SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
- /* reloc */
- *((uint64_t *) &surf[8]) = (bo ? bo->offset64 : 0) + buffer_offset;
-
- /* Emit relocation to surface contents. */
- if (bo) {
- drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 8 * 4,
- bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
- rw ? I915_GEM_DOMAIN_SAMPLER : 0);
- }
-}
-
-static void
-gen8_update_texture_surface(struct gl_context *ctx,
- unsigned unit,
- uint32_t *surf_offset,
- bool for_gather)
-{
- struct brw_context *brw = brw_context(ctx);
- struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
- struct intel_texture_object *intelObj = intel_texture_object(tObj);
- struct intel_mipmap_tree *mt = intelObj->mt;
- struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
- struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
-
- if (tObj->Target == GL_TEXTURE_BUFFER) {
- brw_update_buffer_texture_surface(ctx, unit, surf_offset);
- return;
- }
-
- if (tObj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL)
- mt = mt->stencil_mt;
-
- unsigned tiling_mode, pitch;
- if (mt->format == MESA_FORMAT_S_UINT8) {
- tiling_mode = GEN8_SURFACE_TILING_W;
- pitch = 2 * mt->region->pitch;
- } else {
- tiling_mode = surface_tiling_mode(mt->region->tiling);
- pitch = mt->region->pitch;
- }
-
- uint32_t tex_format = translate_tex_format(brw,
- mt->format,
- sampler->sRGBDecode);
-
- uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 13 * 4, 64, surf_offset);
-
- surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
- tex_format << BRW_SURFACE_FORMAT_SHIFT |
- vertical_alignment(mt) |
- horizontal_alignment(mt) |
- tiling_mode;
-
- if (tObj->Target == GL_TEXTURE_CUBE_MAP ||
- tObj->Target == GL_TEXTURE_CUBE_MAP_ARRAY) {
- surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
- }
-
- if (mt->logical_depth0 > 1 && tObj->Target != GL_TEXTURE_3D)
- surf[0] |= GEN8_SURFACE_IS_ARRAY;
-
- surf[1] = mt->qpitch >> 2;
-
- surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
- SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
-
- surf[3] = SET_FIELD(mt->logical_depth0 - 1, BRW_SURFACE_DEPTH) | (pitch - 1);
-
- surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
-
- surf[5] = SET_FIELD(tObj->BaseLevel - mt->first_level, GEN7_SURFACE_MIN_LOD) |
- (intelObj->_MaxLevel - tObj->BaseLevel); /* mip count */
-
- surf[6] = 0;
-
- /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
- * texturing functions that return a float, as our code generation always
- * selects the .x channel (which would always be 0).
- */
- const bool alpha_depth = tObj->DepthMode == GL_ALPHA &&
- (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
- firstImage->_BaseFormat == GL_DEPTH_STENCIL);
-
- const int swizzle =
- unlikely(alpha_depth) ? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj);
- surf[7] =
- SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 0), false), GEN7_SURFACE_SCS_R) |
- SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 1), false), GEN7_SURFACE_SCS_G) |
- SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 2), false), GEN7_SURFACE_SCS_B) |
- SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 3), false), GEN7_SURFACE_SCS_A);
-
- *((uint64_t *) &surf[8]) = mt->region->bo->offset64 + mt->offset; /* reloc */
-
- surf[10] = 0;
- surf[11] = 0;
- surf[12] = 0;
-
- /* Emit relocation to surface contents */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- *surf_offset + 8 * 4,
- mt->region->bo,
- mt->offset,
- I915_GEM_DOMAIN_SAMPLER, 0);