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i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush.
[mesa.git]
/
src
/
mesa
/
drivers
/
dri
/
i965
/
intel_fbo.c
diff --git
a/src/mesa/drivers/dri/i965/intel_fbo.c
b/src/mesa/drivers/dri/i965/intel_fbo.c
index 939f9a08c58e40a88ba201a9d8e11aebb4b2a0c6..707a9d2af3d88dfab46a9f02a521ea59ac387483 100644
(file)
--- a/
src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/
src/mesa/drivers/dri/i965/intel_fbo.c
@@
-1061,14
+1061,6
@@
brw_render_cache_set_check_flush(struct brw_context *brw, drm_intel_bo *bo)
return;
if (brw->gen >= 6) {
return;
if (brw->gen >= 6) {
- if (brw->gen == 6) {
- /* [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
- * Flush Enable = 1, a PIPE_CONTROL with any non-zero
- * post-sync-op is required.
- */
- brw_emit_post_sync_nonzero_flush(brw);
- }
-
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_RENDER_TARGET_FLUSH |
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_RENDER_TARGET_FLUSH |