+
+enum isl_surf_dim
+get_isl_surf_dim(GLenum target)
+{
+ switch (target) {
+ case GL_TEXTURE_1D:
+ case GL_TEXTURE_1D_ARRAY:
+ return ISL_SURF_DIM_1D;
+
+ case GL_TEXTURE_2D:
+ case GL_TEXTURE_2D_ARRAY:
+ case GL_TEXTURE_RECTANGLE:
+ case GL_TEXTURE_CUBE_MAP:
+ case GL_TEXTURE_CUBE_MAP_ARRAY:
+ case GL_TEXTURE_2D_MULTISAMPLE:
+ case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
+ case GL_TEXTURE_EXTERNAL_OES:
+ return ISL_SURF_DIM_2D;
+
+ case GL_TEXTURE_3D:
+ return ISL_SURF_DIM_3D;
+ }
+
+ unreachable("Invalid texture target");
+}
+
+enum isl_dim_layout
+get_isl_dim_layout(const struct gen_device_info *devinfo, uint32_t tiling,
+ GLenum target)
+{
+ switch (target) {
+ case GL_TEXTURE_1D:
+ case GL_TEXTURE_1D_ARRAY:
+ return (devinfo->gen >= 9 && tiling == I915_TILING_NONE ?
+ ISL_DIM_LAYOUT_GEN9_1D : ISL_DIM_LAYOUT_GEN4_2D);
+
+ case GL_TEXTURE_2D:
+ case GL_TEXTURE_2D_ARRAY:
+ case GL_TEXTURE_RECTANGLE:
+ case GL_TEXTURE_2D_MULTISAMPLE:
+ case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
+ case GL_TEXTURE_EXTERNAL_OES:
+ return ISL_DIM_LAYOUT_GEN4_2D;
+
+ case GL_TEXTURE_CUBE_MAP:
+ case GL_TEXTURE_CUBE_MAP_ARRAY:
+ return (devinfo->gen == 4 ? ISL_DIM_LAYOUT_GEN4_3D :
+ ISL_DIM_LAYOUT_GEN4_2D);
+
+ case GL_TEXTURE_3D:
+ return (devinfo->gen >= 9 ?
+ ISL_DIM_LAYOUT_GEN4_2D : ISL_DIM_LAYOUT_GEN4_3D);
+ }
+
+ unreachable("Invalid texture target");
+}
+
+enum isl_tiling
+intel_miptree_get_isl_tiling(const struct intel_mipmap_tree *mt)
+{
+ if (mt->format == MESA_FORMAT_S_UINT8) {
+ return ISL_TILING_W;
+ } else {
+ switch (mt->tiling) {
+ case I915_TILING_NONE:
+ return ISL_TILING_LINEAR;
+ case I915_TILING_X:
+ return ISL_TILING_X;
+ case I915_TILING_Y:
+ switch (mt->tr_mode) {
+ case INTEL_MIPTREE_TRMODE_NONE:
+ return ISL_TILING_Y0;
+ case INTEL_MIPTREE_TRMODE_YF:
+ return ISL_TILING_Yf;
+ case INTEL_MIPTREE_TRMODE_YS:
+ return ISL_TILING_Ys;
+ default:
+ unreachable("Invalid tiled resource mode");
+ }
+ default:
+ unreachable("Invalid tiling mode");
+ }
+ }
+}
+
+void
+intel_miptree_get_isl_surf(struct brw_context *brw,
+ const struct intel_mipmap_tree *mt,
+ struct isl_surf *surf)
+{
+ surf->dim = get_isl_surf_dim(mt->target);
+ surf->dim_layout = get_isl_dim_layout(&brw->screen->devinfo,
+ mt->tiling, mt->target);
+
+ if (mt->num_samples > 1) {
+ switch (mt->msaa_layout) {
+ case INTEL_MSAA_LAYOUT_IMS:
+ surf->msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED;
+ break;
+ case INTEL_MSAA_LAYOUT_UMS:
+ case INTEL_MSAA_LAYOUT_CMS:
+ surf->msaa_layout = ISL_MSAA_LAYOUT_ARRAY;
+ break;
+ default:
+ unreachable("Invalid MSAA layout");
+ }
+ } else {
+ surf->msaa_layout = ISL_MSAA_LAYOUT_NONE;
+ }
+
+ surf->tiling = intel_miptree_get_isl_tiling(mt);
+
+ if (mt->format == MESA_FORMAT_S_UINT8) {
+ /* The ISL definition of row_pitch matches the surface state pitch field
+ * a bit better than intel_mipmap_tree. In particular, ISL incorporates
+ * the factor of 2 for W-tiling in row_pitch.
+ */
+ surf->row_pitch = 2 * mt->pitch;
+ } else {
+ surf->row_pitch = mt->pitch;
+ }
+
+ surf->format = translate_tex_format(brw, mt->format, false);
+
+ if (brw->gen >= 9) {
+ if (surf->dim == ISL_SURF_DIM_1D && surf->tiling == ISL_TILING_LINEAR) {
+ /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
+ surf->image_alignment_el = isl_extent3d(64, 1, 1);
+ } else {
+ /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
+ * alignment in terms of surface elements like we want.
+ */
+ surf->image_alignment_el = isl_extent3d(mt->halign, mt->valign, 1);
+ }
+ } else {
+ /* On earlier gens it's stored in pixels. */
+ unsigned bw, bh;
+ _mesa_get_format_block_size(mt->format, &bw, &bh);
+ surf->image_alignment_el =
+ isl_extent3d(mt->halign / bw, mt->valign / bh, 1);
+ }
+
+ surf->logical_level0_px.width = mt->logical_width0;
+ surf->logical_level0_px.height = mt->logical_height0;
+ if (surf->dim == ISL_SURF_DIM_3D) {
+ surf->logical_level0_px.depth = mt->logical_depth0;
+ surf->logical_level0_px.array_len = 1;
+ } else {
+ surf->logical_level0_px.depth = 1;
+ surf->logical_level0_px.array_len = mt->logical_depth0;
+ }
+
+ surf->phys_level0_sa.width = mt->physical_width0;
+ surf->phys_level0_sa.height = mt->physical_height0;
+ if (surf->dim == ISL_SURF_DIM_3D) {
+ surf->phys_level0_sa.depth = mt->physical_depth0;
+ surf->phys_level0_sa.array_len = 1;
+ } else {
+ surf->phys_level0_sa.depth = 1;
+ surf->phys_level0_sa.array_len = mt->physical_depth0;
+ }
+
+ surf->levels = mt->last_level + 1;
+ surf->samples = MAX2(mt->num_samples, 1);
+
+ surf->size = 0; /* TODO */
+ surf->alignment = 0; /* TODO */
+
+ switch (surf->dim_layout) {
+ case ISL_DIM_LAYOUT_GEN4_2D:
+ case ISL_DIM_LAYOUT_GEN4_3D:
+ if (brw->gen >= 9) {
+ surf->array_pitch_el_rows = mt->qpitch;
+ } else {
+ unsigned bw, bh;
+ _mesa_get_format_block_size(mt->format, &bw, &bh);
+ assert(mt->qpitch % bh == 0);
+ surf->array_pitch_el_rows = mt->qpitch / bh;
+ }
+ break;
+ case ISL_DIM_LAYOUT_GEN9_1D:
+ surf->array_pitch_el_rows = 1;
+ break;
+ }
+
+ switch (mt->array_layout) {
+ case ALL_LOD_IN_EACH_SLICE:
+ surf->array_pitch_span = ISL_ARRAY_PITCH_SPAN_FULL;
+ break;
+ case ALL_SLICES_AT_EACH_LOD:
+ surf->array_pitch_span = ISL_ARRAY_PITCH_SPAN_COMPACT;
+ break;
+ default:
+ unreachable("Invalid array layout");
+ }
+
+ GLenum base_format = _mesa_get_format_base_format(mt->format);
+ switch (base_format) {
+ case GL_DEPTH_COMPONENT:
+ surf->usage = ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_TEXTURE_BIT;
+ break;
+ case GL_STENCIL_INDEX:
+ surf->usage = ISL_SURF_USAGE_STENCIL_BIT;
+ if (brw->gen >= 8)
+ surf->usage |= ISL_SURF_USAGE_TEXTURE_BIT;
+ break;
+ case GL_DEPTH_STENCIL:
+ /* In this case we only texture from the depth part */
+ surf->usage = ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT |
+ ISL_SURF_USAGE_TEXTURE_BIT;
+ break;
+ default:
+ surf->usage = ISL_SURF_USAGE_TEXTURE_BIT;
+ if (brw->format_supported_as_render_target[mt->format])
+ surf->usage = ISL_SURF_USAGE_RENDER_TARGET_BIT;
+ break;
+ }
+
+ if (_mesa_is_cube_map_texture(mt->target))
+ surf->usage |= ISL_SURF_USAGE_CUBE_BIT;
+}
+
+/* WARNING: THE SURFACE CREATED BY THIS FUNCTION IS NOT COMPLETE AND CANNOT BE
+ * USED FOR ANY REAL CALCULATIONS. THE ONLY VALID USE OF SUCH A SURFACE IS TO
+ * PASS IT INTO isl_surf_fill_state.
+ */
+void
+intel_miptree_get_aux_isl_surf(struct brw_context *brw,
+ const struct intel_mipmap_tree *mt,
+ struct isl_surf *surf,
+ enum isl_aux_usage *usage)
+{
+ uint32_t aux_pitch, aux_qpitch;
+ if (mt->mcs_buf) {
+ aux_pitch = mt->mcs_buf->mt->pitch;
+ aux_qpitch = mt->mcs_buf->mt->qpitch;
+
+ if (mt->num_samples > 1) {
+ assert(mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS);
+ *usage = ISL_AUX_USAGE_MCS;
+ } else if (intel_miptree_is_lossless_compressed(brw, mt)) {
+ assert(brw->gen >= 9);
+ *usage = ISL_AUX_USAGE_CCS_E;
+ } else if (mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_NO_MCS) {
+ *usage = ISL_AUX_USAGE_CCS_D;
+ } else {
+ unreachable("Invalid MCS miptree");
+ }
+ } else if (mt->hiz_buf) {
+ if (mt->hiz_buf->mt) {
+ aux_pitch = mt->hiz_buf->mt->pitch;
+ aux_qpitch = mt->hiz_buf->mt->qpitch;
+ } else {
+ aux_pitch = mt->hiz_buf->pitch;
+ aux_qpitch = mt->hiz_buf->qpitch;
+ }
+
+ *usage = ISL_AUX_USAGE_HIZ;
+ } else {
+ *usage = ISL_AUX_USAGE_NONE;
+ return;
+ }
+
+ /* Start with a copy of the original surface. */
+ intel_miptree_get_isl_surf(brw, mt, surf);
+
+ /* Figure out the format and tiling of the auxiliary surface */
+ switch (*usage) {
+ case ISL_AUX_USAGE_NONE:
+ unreachable("Invalid auxiliary usage");
+
+ case ISL_AUX_USAGE_HIZ:
+ isl_surf_get_hiz_surf(&brw->isl_dev, surf, surf);
+ break;
+
+ case ISL_AUX_USAGE_MCS:
+ /*
+ * From the SKL PRM:
+ * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
+ * HALIGN 16 must be used."
+ */
+ if (brw->gen >= 9)
+ assert(mt->halign == 16);
+
+ isl_surf_get_mcs_surf(&brw->isl_dev, surf, surf);
+ break;
+
+ case ISL_AUX_USAGE_CCS_D:
+ case ISL_AUX_USAGE_CCS_E:
+ /*
+ * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
+ *
+ * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
+ *
+ * From the hardware spec for GEN9:
+ *
+ * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
+ * HALIGN 16 must be used."
+ */
+ assert(mt->num_samples <= 1);
+ if (brw->gen >= 8)
+ assert(mt->halign == 16);
+
+ isl_surf_get_ccs_surf(&brw->isl_dev, surf, surf);
+ break;
+ }
+
+ /* We want the pitch of the actual aux buffer. */
+ surf->row_pitch = aux_pitch;
+
+ /* Auxiliary surfaces in ISL have compressed formats and array_pitch_el_rows
+ * is in elements. This doesn't match intel_mipmap_tree::qpitch which is
+ * in elements of the primary color surface so we have to divide by the
+ * compression block height.
+ */
+ surf->array_pitch_el_rows =
+ aux_qpitch / isl_format_get_layout(surf->format)->bh;
+}
+
+union isl_color_value
+intel_miptree_get_isl_clear_color(struct brw_context *brw,
+ const struct intel_mipmap_tree *mt)
+{
+ union isl_color_value clear_color;
+
+ if (_mesa_get_format_base_format(mt->format) == GL_DEPTH_COMPONENT) {
+ clear_color.i32[0] = mt->depth_clear_value;
+ clear_color.i32[1] = 0;
+ clear_color.i32[2] = 0;
+ clear_color.i32[3] = 0;
+ } else if (brw->gen >= 9) {
+ clear_color.i32[0] = mt->gen9_fast_clear_color.i[0];
+ clear_color.i32[1] = mt->gen9_fast_clear_color.i[1];
+ clear_color.i32[2] = mt->gen9_fast_clear_color.i[2];
+ clear_color.i32[3] = mt->gen9_fast_clear_color.i[3];
+ } else if (_mesa_is_format_integer(mt->format)) {
+ clear_color.i32[0] = (mt->fast_clear_color_value & (1u << 31)) != 0;
+ clear_color.i32[1] = (mt->fast_clear_color_value & (1u << 30)) != 0;
+ clear_color.i32[2] = (mt->fast_clear_color_value & (1u << 29)) != 0;
+ clear_color.i32[3] = (mt->fast_clear_color_value & (1u << 28)) != 0;
+ } else {
+ clear_color.f32[0] = (mt->fast_clear_color_value & (1u << 31)) != 0;
+ clear_color.f32[1] = (mt->fast_clear_color_value & (1u << 30)) != 0;
+ clear_color.f32[2] = (mt->fast_clear_color_value & (1u << 29)) != 0;
+ clear_color.f32[3] = (mt->fast_clear_color_value & (1u << 28)) != 0;
+ }
+
+ return clear_color;
+}