- mt->aux_state = aux_state;
-
- intel_miptree_init_mcs(brw, mt, 0xFF);
-
- return true;
-}
-
-bool
-intel_miptree_alloc_ccs(struct brw_context *brw,
- struct intel_mipmap_tree *mt)
-{
- assert(mt->mcs_buf == NULL);
- assert(mt->aux_usage == ISL_AUX_USAGE_CCS_E ||
- mt->aux_usage == ISL_AUX_USAGE_CCS_D);
-
- struct isl_surf temp_ccs_surf;
-
- if (!isl_surf_get_ccs_surf(&brw->isl_dev, &mt->surf, &temp_ccs_surf, 0))
- return false;
-
- assert(temp_ccs_surf.size &&
- (temp_ccs_surf.size % temp_ccs_surf.row_pitch == 0));
-
- enum isl_aux_state **aux_state =
- create_aux_state_map(mt, ISL_AUX_STATE_PASS_THROUGH);
- if (!aux_state)
- return false;
-
- /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
- * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
- *
- * "If Software wants to enable Color Compression without Fast clear,
- * Software needs to initialize MCS with zeros."
- *
- * A CCS value of 0 indicates that the corresponding block is in the
- * pass-through state which is what we want.
- *
- * For CCS_D, on the other hand, we don't care as we're about to perform a
- * fast-clear operation. In that case, being hot in caches more useful.
- */
- const uint32_t alloc_flags = mt->aux_usage == ISL_AUX_USAGE_CCS_E ?
- BO_ALLOC_ZEROED : BO_ALLOC_BUSY;
- mt->mcs_buf = intel_alloc_aux_buffer(brw, "ccs-miptree",
- &temp_ccs_surf, alloc_flags, mt);
- if (!mt->mcs_buf) {
- free(aux_state);
- return false;