+/**
+ * Miptree aux buffer. These buffers are associated with a miptree, but the
+ * format is managed by the hardware.
+ *
+ * For Gen7+, we always give the hardware the start of the buffer, and let it
+ * handle all accesses to the buffer. Therefore we don't need the full miptree
+ * layout structure for this buffer.
+ *
+ * For Gen6, we need a hiz miptree structure for this buffer so we can program
+ * offsets to slices & miplevels.
+ */
+struct intel_miptree_aux_buffer
+{
+ /**
+ * Buffer object containing the pixel data.
+ *
+ * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
+ * @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress
+ */
+ drm_intel_bo *bo;
+
+ /**
+ * Pitch in bytes.
+ *
+ * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
+ * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
+ */
+ uint32_t pitch;
+
+ /**
+ * The distance in rows between array slices.
+ *
+ * @see RENDER_SURFACE_STATE.AuxiliarySurfaceQPitch
+ * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
+ */
+ uint32_t qpitch;
+
+ /**
+ * Hiz miptree. Used only by Gen6.
+ */
+ struct intel_mipmap_tree *mt;
+};
+
+/* Tile resource modes */
+enum intel_miptree_tr_mode {
+ INTEL_MIPTREE_TRMODE_NONE,
+ INTEL_MIPTREE_TRMODE_YF,
+ INTEL_MIPTREE_TRMODE_YS
+};
+