+static int
+intel_detect_timestamp(struct intel_screen *screen)
+{
+ uint64_t dummy = 0, last = 0;
+ int upper, lower, loops;
+
+ /* On 64bit systems, some old kernels trigger a hw bug resulting in the
+ * TIMESTAMP register being shifted and the low 32bits always zero.
+ *
+ * More recent kernels offer an interface to read the full 36bits
+ * everywhere.
+ */
+ if (drm_intel_reg_read(screen->bufmgr, TIMESTAMP | 1, &dummy) == 0)
+ return 3;
+
+ /* Determine if we have a 32bit or 64bit kernel by inspecting the
+ * upper 32bits for a rapidly changing timestamp.
+ */
+ if (drm_intel_reg_read(screen->bufmgr, TIMESTAMP, &last))
+ return 0;
+
+ upper = lower = 0;
+ for (loops = 0; loops < 10; loops++) {
+ /* The TIMESTAMP should change every 80ns, so several round trips
+ * through the kernel should be enough to advance it.
+ */
+ if (drm_intel_reg_read(screen->bufmgr, TIMESTAMP, &dummy))
+ return 0;
+
+ upper += (dummy >> 32) != (last >> 32);
+ if (upper > 1) /* beware 32bit counter overflow */
+ return 2; /* upper dword holds the low 32bits of the timestamp */
+
+ lower += (dummy & 0xffffffff) != (last & 0xffffffff);
+ if (lower > 1)
+ return 1; /* timestamp is unshifted */
+
+ last = dummy;
+ }
+
+ /* No advancement? No timestamp! */
+ return 0;
+}
+
+/**
+ * Return array of MSAA modes supported by the hardware. The array is
+ * zero-terminated and sorted in decreasing order.
+ */
+const int*
+intel_supported_msaa_modes(const struct intel_screen *screen)
+{
+ static const int gen8_modes[] = {8, 4, 2, 0, -1};
+ static const int gen7_modes[] = {8, 4, 0, -1};
+ static const int gen6_modes[] = {4, 0, -1};
+ static const int gen4_modes[] = {0, -1};
+
+ if (screen->devinfo->gen >= 8) {
+ return gen8_modes;
+ } else if (screen->devinfo->gen >= 7) {
+ return gen7_modes;
+ } else if (screen->devinfo->gen == 6) {
+ return gen6_modes;
+ } else {
+ return gen4_modes;
+ }
+}
+