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i965: Use {} to initialize GENX_* structs.
[mesa.git]
/
src
/
mesa
/
drivers
/
dri
/
i965
/
intel_tex.c
diff --git
a/src/mesa/drivers/dri/i965/intel_tex.c
b/src/mesa/drivers/dri/i965/intel_tex.c
index a802d5a91867138f42b3f267f79c10f2119b9e29..7ce2ceb9a2f7f72e555d34a5ccd5adccaa7284d3 100644
(file)
--- a/
src/mesa/drivers/dri/i965/intel_tex.c
+++ b/
src/mesa/drivers/dri/i965/intel_tex.c
@@
-5,11
+5,11
@@
#include "main/mipmap.h"
#include "drivers/common/meta.h"
#include "brw_context.h"
#include "main/mipmap.h"
#include "drivers/common/meta.h"
#include "brw_context.h"
+#include "brw_defines.h"
#include "intel_buffer_objects.h"
#include "intel_mipmap_tree.h"
#include "intel_tex.h"
#include "intel_fbo.h"
#include "intel_buffer_objects.h"
#include "intel_mipmap_tree.h"
#include "intel_tex.h"
#include "intel_fbo.h"
-#include "intel_reg.h"
#define FILE_DEBUG_FLAG DEBUG_TEXTURE
#define FILE_DEBUG_FLAG DEBUG_TEXTURE
@@
-71,7
+71,7
@@
intel_alloc_texture_image_buffer(struct gl_context *ctx,
/* Quantize sample count */
if (image->NumSamples) {
/* Quantize sample count */
if (image->NumSamples) {
- image->NumSamples = intel_quantize_num_samples(brw->
intelS
creen, image->NumSamples);
+ image->NumSamples = intel_quantize_num_samples(brw->
s
creen, image->NumSamples);
if (!image->NumSamples)
return false;
}
if (!image->NumSamples)
return false;
}
@@
-94,7
+94,9
@@
intel_alloc_texture_image_buffer(struct gl_context *ctx,
} else {
intel_image->mt = intel_miptree_create_for_teximage(brw, intel_texobj,
intel_image,
} else {
intel_image->mt = intel_miptree_create_for_teximage(brw, intel_texobj,
intel_image,
- 0);
+ 1 /* samples */);
+ if (!intel_image->mt)
+ return false;
/* Even if the object currently has a mipmap tree associated
* with it, this one is a more likely candidate to represent the
/* Even if the object currently has a mipmap tree associated
* with it, this one is a more likely candidate to represent the
@@
-128,7
+130,7
@@
intel_alloc_texture_storage(struct gl_context *ctx,
struct brw_context *brw = brw_context(ctx);
struct intel_texture_object *intel_texobj = intel_texture_object(texobj);
struct gl_texture_image *first_image = texobj->Image[0][0];
struct brw_context *brw = brw_context(ctx);
struct intel_texture_object *intel_texobj = intel_texture_object(texobj);
struct gl_texture_image *first_image = texobj->Image[0][0];
- int num_samples = intel_quantize_num_samples(brw->
intelS
creen,
+ int num_samples = intel_quantize_num_samples(brw->
s
creen,
first_image->NumSamples);
const int numFaces = _mesa_num_tex_faces(texobj->Target);
int face;
first_image->NumSamples);
const int numFaces = _mesa_num_tex_faces(texobj->Target);
int face;
@@
-141,11
+143,13
@@
intel_alloc_texture_storage(struct gl_context *ctx,
!intel_miptree_match_image(intel_texobj->mt, first_image) ||
intel_texobj->mt->last_level != levels - 1) {
intel_miptree_release(&intel_texobj->mt);
!intel_miptree_match_image(intel_texobj->mt, first_image) ||
intel_texobj->mt->last_level != levels - 1) {
intel_miptree_release(&intel_texobj->mt);
+
+ intel_get_image_dims(first_image, &width, &height, &depth);
intel_texobj->mt = intel_miptree_create(brw, texobj->Target,
first_image->TexFormat,
0, levels - 1,
width, height, depth,
intel_texobj->mt = intel_miptree_create(brw, texobj->Target,
first_image->TexFormat,
0, levels - 1,
width, height, depth,
-
num_samples
,
+
MAX2(num_samples, 1)
,
MIPTREE_LAYOUT_TILING_ANY);
if (intel_texobj->mt == NULL) {
MIPTREE_LAYOUT_TILING_ANY);
if (intel_texobj->mt == NULL) {
@@
-323,7
+327,7
@@
intel_set_texture_storage_for_buffer_object(struct gl_context *ctx,
return false;
}
return false;
}
- if (!brw->
format_supported_as_render_target
[image->TexFormat]) {
+ if (!brw->
mesa_format_supports_render
[image->TexFormat]) {
perf_debug("Non-renderable PBO format; fallback to CPU mapping\n");
return false;
}
perf_debug("Non-renderable PBO format; fallback to CPU mapping\n");
return false;
}
@@
-331,9
+335,10
@@
intel_set_texture_storage_for_buffer_object(struct gl_context *ctx,
assert(intel_texobj->mt == NULL);
assert(intel_texobj->mt == NULL);
-
drm_intel
_bo *bo = intel_bufferobj_buffer(brw, intel_buffer_obj,
+
struct brw
_bo *bo = intel_bufferobj_buffer(brw, intel_buffer_obj,
buffer_offset,
buffer_offset,
- row_stride * image->Height);
+ row_stride * image->Height,
+ !read_only);
intel_texobj->mt =
intel_miptree_create_for_bo(brw, bo,
image->TexFormat,
intel_texobj->mt =
intel_miptree_create_for_bo(brw, bo,
image->TexFormat,
@@
-364,14
+369,6
@@
intel_texture_barrier(struct gl_context *ctx)
struct brw_context *brw = brw_context(ctx);
if (brw->gen >= 6) {
struct brw_context *brw = brw_context(ctx);
if (brw->gen >= 6) {
- if (brw->gen == 6) {
- /* [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
- * Flush Enable = 1, a PIPE_CONTROL with any non-zero
- * post-sync-op is required.
- */
- brw_emit_post_sync_nonzero_flush(brw);
- }
-
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_RENDER_TARGET_FLUSH |
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_RENDER_TARGET_FLUSH |