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Merge branch 'lp-offset-twoside'
[mesa.git]
/
src
/
mesa
/
drivers
/
dri
/
intel
/
intel_reg.h
diff --git
a/src/mesa/drivers/dri/intel/intel_reg.h
b/src/mesa/drivers/dri/intel/intel_reg.h
index d19f1bae34ce36e67aeac359c79fdc606d04bc58..955b100b212e088b921badfebcd397665e42c434 100644
(file)
--- a/
src/mesa/drivers/dri/intel/intel_reg.h
+++ b/
src/mesa/drivers/dri/intel/intel_reg.h
@@
-55,6
+55,11
@@
* additional flushing control.
*/
#define _3DSTATE_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24) | 2)
* additional flushing control.
*/
#define _3DSTATE_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24) | 2)
+#define PIPE_CONTROL_CS_STALL (1 << 20)
+#define PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET (1 << 19)
+#define PIPE_CONTROL_TLB_INVALIDATE (1 << 18)
+#define PIPE_CONTROL_SYNC_GFDT (1 << 17)
+#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1 << 16)
#define PIPE_CONTROL_NO_WRITE (0 << 14)
#define PIPE_CONTROL_WRITE_IMMEDIATE (1 << 14)
#define PIPE_CONTROL_WRITE_DEPTH_COUNT (2 << 14)
#define PIPE_CONTROL_NO_WRITE (0 << 14)
#define PIPE_CONTROL_WRITE_IMMEDIATE (1 << 14)
#define PIPE_CONTROL_WRITE_DEPTH_COUNT (2 << 14)
@@
-62,7
+67,14
@@
#define PIPE_CONTROL_DEPTH_STALL (1 << 13)
#define PIPE_CONTROL_WRITE_FLUSH (1 << 12)
#define PIPE_CONTROL_INSTRUCTION_FLUSH (1 << 11)
#define PIPE_CONTROL_DEPTH_STALL (1 << 13)
#define PIPE_CONTROL_WRITE_FLUSH (1 << 12)
#define PIPE_CONTROL_INSTRUCTION_FLUSH (1 << 11)
+#define PIPE_CONTROL_TC_FLUSH (1 << 10) /* GM45+ only */
+#define PIPE_CONTROL_ISP_DIS (1 << 9)
#define PIPE_CONTROL_INTERRUPT_ENABLE (1 << 8)
#define PIPE_CONTROL_INTERRUPT_ENABLE (1 << 8)
+/* GT */
+#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1 << 4)
+#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1 << 3)
+#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1 << 2)
+#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0)
#define PIPE_CONTROL_PPGTT_WRITE (0 << 2)
#define PIPE_CONTROL_GLOBAL_GTT_WRITE (1 << 2)
#define PIPE_CONTROL_PPGTT_WRITE (0 << 2)
#define PIPE_CONTROL_GLOBAL_GTT_WRITE (1 << 2)
@@
-70,8
+82,10
@@
/** @{
* 915 definitions
/** @{
* 915 definitions
+ *
+ * 915 documents say that bits 31:28 and 1 are "undefined, must be zero."
*/
*/
-#define S0_VB_OFFSET_MASK 0x
ffffffc0
+#define S0_VB_OFFSET_MASK 0x
0ffffffc
#define S0_AUTO_CACHE_INV_DISABLE (1<<0)
/** @} */
#define S0_AUTO_CACHE_INV_DISABLE (1<<0)
/** @} */
@@
-237,6
+251,7
@@
#define XY_DST_TILED (1 << 11)
/* BR13 */
#define XY_DST_TILED (1 << 11)
/* BR13 */
+#define BR13_8 (0x0 << 24)
#define BR13_565 (0x1 << 24)
#define BR13_8888 (0x3 << 24)
#define BR13_565 (0x1 << 24)
#define BR13_8888 (0x3 << 24)