+ switch (dst_mesa_format) {
+ case MESA_FORMAT_ARGB8888:
+ case MESA_FORMAT_XRGB8888:
+ case MESA_FORMAT_RGB565:
+ case MESA_FORMAT_ARGB4444:
+ case MESA_FORMAT_ARGB1555:
+ case MESA_FORMAT_A8:
+ case MESA_FORMAT_L8:
+ case MESA_FORMAT_I8:
+ default:
+ /* no swizzle required */
+ BEGIN_BATCH(10);
+ OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE |
+ RADEON_TEX_BLEND_0_ENABLE));
+ OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO |
+ R200_TXC_ARG_B_ZERO |
+ R200_TXC_ARG_C_R0_COLOR |
+ R200_TXC_OP_MADD));
+ OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 |
+ R200_TXC_OUTPUT_REG_R0));
+ OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO |
+ R200_TXA_ARG_B_ZERO |
+ R200_TXA_ARG_C_R0_ALPHA |
+ R200_TXA_OP_MADD));
+ OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, (R200_TXA_CLAMP_0_1 |
+ R200_TXA_OUTPUT_REG_R0));
+ END_BATCH();
+ break;
+ case MESA_FORMAT_RGBA8888:
+ BEGIN_BATCH(10);
+ OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE |
+ RADEON_TEX_BLEND_0_ENABLE));
+ OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO |
+ R200_TXC_ARG_B_ZERO |
+ R200_TXC_ARG_C_R0_COLOR |
+ R200_TXC_OP_MADD));
+ OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 |
+ R200_TXC_OUTPUT_ROTATE_GBA |
+ R200_TXC_OUTPUT_REG_R0));
+ OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO |
+ R200_TXA_ARG_B_ZERO |
+ R200_TXA_ARG_C_R0_ALPHA |
+ R200_TXA_OP_MADD));
+ OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, (R200_TXA_CLAMP_0_1 |
+ (R200_TXA_REPL_RED << R200_TXA_REPL_ARG_C_SHIFT) |
+ R200_TXA_OUTPUT_REG_R0));
+ END_BATCH();
+ break;
+ case MESA_FORMAT_RGBA8888_REV:
+ BEGIN_BATCH(34);
+ OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE |
+ RADEON_TEX_BLEND_0_ENABLE |
+ RADEON_TEX_BLEND_1_ENABLE |
+ RADEON_TEX_BLEND_2_ENABLE |
+ RADEON_TEX_BLEND_3_ENABLE));
+ /* r1.r = r0.b */
+ OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO |
+ R200_TXC_ARG_B_ZERO |
+ R200_TXC_ARG_C_R0_COLOR |
+ R200_TXC_OP_MADD));
+ OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 |
+ R200_TXC_OUTPUT_MASK_R |
+ (R200_TXC_REPL_BLUE << R200_TXC_REPL_ARG_C_SHIFT) |
+ R200_TXC_OUTPUT_REG_R1));
+ /* r1.a = r0.a */
+ OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO |
+ R200_TXA_ARG_B_ZERO |
+ R200_TXA_ARG_C_R0_ALPHA |
+ R200_TXA_OP_MADD));
+ OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, (R200_TXA_CLAMP_0_1 |
+ R200_TXA_OUTPUT_REG_R1));
+ /* r1.g = r0.g */
+ OUT_BATCH_REGVAL(R200_PP_TXCBLEND_1, (R200_TXC_ARG_A_ZERO |
+ R200_TXC_ARG_B_ZERO |
+ R200_TXC_ARG_C_R0_COLOR |
+ R200_TXC_OP_MADD));
+ OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_1, (R200_TXC_CLAMP_0_1 |
+ R200_TXC_OUTPUT_MASK_G |
+ (R200_TXC_REPL_GREEN << R200_TXC_REPL_ARG_C_SHIFT) |
+ R200_TXC_OUTPUT_REG_R1));
+ /* r1.a = r0.a */
+ OUT_BATCH_REGVAL(R200_PP_TXABLEND_1, (R200_TXA_ARG_A_ZERO |
+ R200_TXA_ARG_B_ZERO |
+ R200_TXA_ARG_C_R0_ALPHA |
+ R200_TXA_OP_MADD));
+ OUT_BATCH_REGVAL(R200_PP_TXABLEND2_1, (R200_TXA_CLAMP_0_1 |
+ R200_TXA_OUTPUT_REG_R1));
+ /* r1.b = r0.r */
+ OUT_BATCH_REGVAL(R200_PP_TXCBLEND_2, (R200_TXC_ARG_A_ZERO |
+ R200_TXC_ARG_B_ZERO |
+ R200_TXC_ARG_C_R0_COLOR |
+ R200_TXC_OP_MADD));
+ OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_2, (R200_TXC_CLAMP_0_1 |
+ R200_TXC_OUTPUT_MASK_B |
+ (R200_TXC_REPL_RED << R200_TXC_REPL_ARG_C_SHIFT) |
+ R200_TXC_OUTPUT_REG_R1));
+ /* r1.a = r0.a */
+ OUT_BATCH_REGVAL(R200_PP_TXABLEND_2, (R200_TXA_ARG_A_ZERO |
+ R200_TXA_ARG_B_ZERO |
+ R200_TXA_ARG_C_R0_ALPHA |
+ R200_TXA_OP_MADD));
+ OUT_BATCH_REGVAL(R200_PP_TXABLEND2_2, (R200_TXA_CLAMP_0_1 |
+ R200_TXA_OUTPUT_REG_R1));
+ /* r0.rgb = r1.rgb */
+ OUT_BATCH_REGVAL(R200_PP_TXCBLEND_3, (R200_TXC_ARG_A_ZERO |
+ R200_TXC_ARG_B_ZERO |
+ R200_TXC_ARG_C_R1_COLOR |
+ R200_TXC_OP_MADD));
+ OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_3, (R200_TXC_CLAMP_0_1 |
+ R200_TXC_OUTPUT_REG_R0));
+ /* r0.a = r1.a */
+ OUT_BATCH_REGVAL(R200_PP_TXABLEND_3, (R200_TXA_ARG_A_ZERO |
+ R200_TXA_ARG_B_ZERO |
+ R200_TXA_ARG_C_R1_ALPHA |
+ R200_TXA_OP_MADD));
+ OUT_BATCH_REGVAL(R200_PP_TXABLEND2_3, (R200_TXA_CLAMP_0_1 |
+ R200_TXA_OUTPUT_REG_R0));
+ END_BATCH();
+ break;
+ }
+
+ BEGIN_BATCH(18);