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Drop GLcontext typedef and use struct gl_context instead
[mesa.git]
/
src
/
mesa
/
drivers
/
dri
/
r200
/
r200_state_init.c
diff --git
a/src/mesa/drivers/dri/r200/r200_state_init.c
b/src/mesa/drivers/dri/r200/r200_state_init.c
index 4c484d067ee1344041cab41c1b4a7db99253e8df..f6afb90d595cb01709c5222f8dbbec4338155401 100644
(file)
--- a/
src/mesa/drivers/dri/r200/r200_state_init.c
+++ b/
src/mesa/drivers/dri/r200/r200_state_init.c
@@
-39,7
+39,6
@@
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "swrast/swrast.h"
#include "vbo/vbo.h"
#include "swrast/swrast.h"
#include "vbo/vbo.h"
-#include "tnl/tnl.h"
#include "tnl/t_pipeline.h"
#include "swrast_setup/swrast_setup.h"
#include "tnl/t_pipeline.h"
#include "swrast_setup/swrast_setup.h"
@@
-48,9
+47,6
@@
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "r200_context.h"
#include "r200_ioctl.h"
#include "r200_state.h"
#include "r200_context.h"
#include "r200_ioctl.h"
#include "r200_state.h"
-#include "r200_tcl.h"
-#include "r200_tex.h"
-#include "r200_swtcl.h"
#include "radeon_queryobj.h"
#include "xmlpool.h"
#include "radeon_queryobj.h"
#include "xmlpool.h"
@@
-232,7
+228,7
@@
static int cmdscl2( int offset, int stride, int count )
* If it is active check function returns maximum emit size.
*/
#define CHECK( NM, FLAG, ADD ) \
* If it is active check function returns maximum emit size.
*/
#define CHECK( NM, FLAG, ADD ) \
-static int check_##NM(
GL
context *ctx, struct radeon_state_atom *atom) \
+static int check_##NM(
struct gl_
context *ctx, struct radeon_state_atom *atom) \
{ \
r200ContextPtr rmesa = R200_CONTEXT(ctx); \
(void) rmesa; \
{ \
r200ContextPtr rmesa = R200_CONTEXT(ctx); \
(void) rmesa; \
@@
-240,21
+236,21
@@
static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
}
#define TCL_CHECK( NM, FLAG, ADD ) \
}
#define TCL_CHECK( NM, FLAG, ADD ) \
-static int check_##NM(
GL
context *ctx, struct radeon_state_atom *atom) \
+static int check_##NM(
struct gl_
context *ctx, struct radeon_state_atom *atom) \
{ \
r200ContextPtr rmesa = R200_CONTEXT(ctx); \
return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
}
#define TCL_OR_VP_CHECK( NM, FLAG, ADD ) \
{ \
r200ContextPtr rmesa = R200_CONTEXT(ctx); \
return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
}
#define TCL_OR_VP_CHECK( NM, FLAG, ADD ) \
-static int check_##NM(
GL
context *ctx, struct radeon_state_atom *atom ) \
+static int check_##NM(
struct gl_
context *ctx, struct radeon_state_atom *atom ) \
{ \
r200ContextPtr rmesa = R200_CONTEXT(ctx); \
return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
}
#define VP_CHECK( NM, FLAG, ADD ) \
{ \
r200ContextPtr rmesa = R200_CONTEXT(ctx); \
return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
}
#define VP_CHECK( NM, FLAG, ADD ) \
-static int check_##NM(
GL
context *ctx, struct radeon_state_atom *atom ) \
+static int check_##NM(
struct gl_
context *ctx, struct radeon_state_atom *atom ) \
{ \
r200ContextPtr rmesa = R200_CONTEXT(ctx); \
(void) atom; \
{ \
r200ContextPtr rmesa = R200_CONTEXT(ctx); \
(void) atom; \
@@
-271,7
+267,7
@@
CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled, 0 )
CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)), 0 )
CHECK( afs, ctx->ATIFragmentShader._Enabled, 0 )
CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 3 + 3*5 - CUBE_STATE_SIZE )
CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)), 0 )
CHECK( afs, ctx->ATIFragmentShader._Enabled, 0 )
CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 3 + 3*5 - CUBE_STATE_SIZE )
-CHECK( tex_cube_cs, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 2 +
2
*5 - CUBE_STATE_SIZE )
+CHECK( tex_cube_cs, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 2 +
4
*5 - CUBE_STATE_SIZE )
TCL_CHECK( tcl_fog, ctx->Fog.Enabled, 0 )
TCL_CHECK( tcl_fog_add4, ctx->Fog.Enabled, 4 )
TCL_CHECK( tcl, GL_TRUE, 0 )
TCL_CHECK( tcl_fog, ctx->Fog.Enabled, 0 )
TCL_CHECK( tcl_fog_add4, ctx->Fog.Enabled, 4 )
TCL_CHECK( tcl, GL_TRUE, 0 )
@@
-341,7
+337,7
@@
VP_CHECK( tcl_vpp_size_add4, ctx->VertexProgram.Current->Base.NumNativeParameter
OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
OUT_BATCH_TABLE((data), h.scalars.count); \
} while(0)
OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
OUT_BATCH_TABLE((data), h.scalars.count); \
} while(0)
-static int check_rrb(
GL
context *ctx, struct radeon_state_atom *atom)
+static int check_rrb(
struct gl_
context *ctx, struct radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
struct radeon_renderbuffer *rrb;
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
struct radeon_renderbuffer *rrb;
@@
-351,7
+347,16
@@
static int check_rrb(GLcontext *ctx, struct radeon_state_atom *atom)
return atom->cmd_size;
}
return atom->cmd_size;
}
-static void mtl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
+static int check_polygon_stipple(struct gl_context *ctx,
+ struct radeon_state_atom *atom)
+{
+ r200ContextPtr r200 = R200_CONTEXT(ctx);
+ if (r200->hw.set.cmd[SET_RE_CNTL] & R200_STIPPLE_ENABLE)
+ return atom->cmd_size;
+ return 0;
+}
+
+static void mtl_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
@@
-363,7
+368,7
@@
static void mtl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
END_BATCH();
}
END_BATCH();
}
-static void lit_emit(
GL
context *ctx, struct radeon_state_atom *atom)
+static void lit_emit(
struct gl_
context *ctx, struct radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
@@
-375,7
+380,7
@@
static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom)
END_BATCH();
}
END_BATCH();
}
-static void ptp_emit(
GL
context *ctx, struct radeon_state_atom *atom)
+static void ptp_emit(
struct gl_
context *ctx, struct radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
@@
-387,7
+392,7
@@
static void ptp_emit(GLcontext *ctx, struct radeon_state_atom *atom)
END_BATCH();
}
END_BATCH();
}
-static void veclinear_emit(
GL
context *ctx, struct radeon_state_atom *atom)
+static void veclinear_emit(
struct gl_
context *ctx, struct radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
@@
-396,7
+401,7
@@
static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom)
OUT_VECLINEAR(atom->cmd[0], atom->cmd+1);
}
OUT_VECLINEAR(atom->cmd[0], atom->cmd+1);
}
-static void scl_emit(
GL
context *ctx, struct radeon_state_atom *atom)
+static void scl_emit(
struct gl_
context *ctx, struct radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
@@
-408,7
+413,7
@@
static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
}
}
-static void vec_emit(
GL
context *ctx, struct radeon_state_atom *atom)
+static void vec_emit(
struct gl_
context *ctx, struct radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
@@
-419,7
+424,7
@@
static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
END_BATCH();
}
END_BATCH();
}
-static void ctx_emit(
GL
context *ctx, struct radeon_state_atom *atom)
+static void ctx_emit(
struct gl_
context *ctx, struct radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
@@
-486,7
+491,7
@@
static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
END_BATCH();
}
END_BATCH();
}
-static int check_always_ctx(
GL
context *ctx, struct radeon_state_atom *atom)
+static int check_always_ctx(
struct gl_
context *ctx, struct radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
struct radeon_renderbuffer *rrb, *drb;
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
struct radeon_renderbuffer *rrb, *drb;
@@
-511,7
+516,7
@@
static int check_always_ctx( GLcontext *ctx, struct radeon_state_atom *atom)
return dwords;
}
return dwords;
}
-static void ctx_emit_cs(
GL
context *ctx, struct radeon_state_atom *atom)
+static void ctx_emit_cs(
struct gl_
context *ctx, struct radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
@@
-529,16
+534,18
@@
static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
if (rrb->cpp == 4)
atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
if (rrb->cpp == 4)
atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
- else switch (rrb->base.
_Actual
Format) {
- case
GL_RGB
5:
+ else switch (rrb->base.Format) {
+ case
MESA_FORMAT_RGB56
5:
atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
break;
atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
break;
- case
GL_RGBA
4:
+ case
MESA_FORMAT_ARGB444
4:
atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444;
break;
atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444;
break;
- case
GL_RGB5_A1
:
+ case
MESA_FORMAT_ARGB1555
:
atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555;
break;
atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555;
break;
+ default:
+ _mesa_problem(ctx, "Unexpected format in ctx_emit_cs");
}
cbpitch = (rrb->pitch / rrb->cpp);
}
cbpitch = (rrb->pitch / rrb->cpp);
@@
-593,7
+600,7
@@
static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
END_BATCH();
}
END_BATCH();
}
-static int get_tex_size(
GL
context* ctx, struct radeon_state_atom *atom)
+static int get_tex_size(
struct gl_
context* ctx, struct radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
uint32_t dwords = atom->cmd_size + 2;
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
uint32_t dwords = atom->cmd_size + 2;
@@
-605,7
+612,7
@@
static int get_tex_size(GLcontext* ctx, struct radeon_state_atom *atom)
return dwords;
}
return dwords;
}
-static int check_tex_pair(
GL
context* ctx, struct radeon_state_atom *atom)
+static int check_tex_pair(
struct gl_
context* ctx, struct radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
/** XOR is bit flip operation so use it for finding pair */
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
/** XOR is bit flip operation so use it for finding pair */
@@
-615,7
+622,7
@@
static int check_tex_pair(GLcontext* ctx, struct radeon_state_atom *atom)
return get_tex_size(ctx, atom);
}
return get_tex_size(ctx, atom);
}
-static int check_tex(
GL
context* ctx, struct radeon_state_atom *atom)
+static int check_tex(
struct gl_
context* ctx, struct radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
if (!(r200->state.texture.unit[atom->idx].unitneeded))
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
if (!(r200->state.texture.unit[atom->idx].unitneeded))
@@
-625,7
+632,7
@@
static int check_tex(GLcontext* ctx, struct radeon_state_atom *atom)
}
}
-static void tex_emit(
GL
context *ctx, struct radeon_state_atom *atom)
+static void tex_emit(
struct gl_
context *ctx, struct radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
@@
-638,7
+645,7
@@
static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
OUT_BATCH_TABLE(atom->cmd, 10);
if (t && t->mt && !t->image_override) {
OUT_BATCH_TABLE(atom->cmd, 10);
if (t && t->mt && !t->image_override) {
- OUT_BATCH_RELOC(t->tile_bits, t->mt->bo,
0
,
+ OUT_BATCH_RELOC(t->tile_bits, t->mt->bo,
get_base_teximage_offset(t)
,
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
} else if (!t) {
/* workaround for old CS mechanism */
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
} else if (!t) {
/* workaround for old CS mechanism */
@@
-650,7
+657,7
@@
static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
END_BATCH();
}
END_BATCH();
}
-static int get_tex_mm_size(
GL
context* ctx, struct radeon_state_atom *atom)
+static int get_tex_mm_size(
struct gl_
context* ctx, struct radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
uint32_t dwords = atom->cmd_size + 2;
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
uint32_t dwords = atom->cmd_size + 2;
@@
-669,7
+676,7
@@
static int get_tex_mm_size(GLcontext* ctx, struct radeon_state_atom *atom)
return dwords;
}
return dwords;
}
-static int check_tex_pair_mm(
GL
context* ctx, struct radeon_state_atom *atom)
+static int check_tex_pair_mm(
struct gl_
context* ctx, struct radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
/** XOR is bit flip operation so use it for finding pair */
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
/** XOR is bit flip operation so use it for finding pair */
@@
-679,7
+686,7
@@
static int check_tex_pair_mm(GLcontext* ctx, struct radeon_state_atom *atom)
return get_tex_mm_size(ctx, atom);
}
return get_tex_mm_size(ctx, atom);
}
-static int check_tex_mm(
GL
context* ctx, struct radeon_state_atom *atom)
+static int check_tex_mm(
struct gl_
context* ctx, struct radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
if (!(r200->state.texture.unit[atom->idx].unitneeded))
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
if (!(r200->state.texture.unit[atom->idx].unitneeded))
@@
-689,14
+696,15
@@
static int check_tex_mm(GLcontext* ctx, struct radeon_state_atom *atom)
}
}
-static void tex_emit_mm(
GL
context *ctx, struct radeon_state_atom *atom)
+static void tex_emit_mm(
struct gl_
context *ctx, struct radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
uint32_t dwords = atom->check(ctx, atom);
int i = atom->idx;
radeonTexObj *t = r200->state.texture.unit[i].texobj;
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
uint32_t dwords = atom->check(ctx, atom);
int i = atom->idx;
radeonTexObj *t = r200->state.texture.unit[i].texobj;
- if (!r200->state.texture.unit[i].unitneeded)
+
+ if (!r200->state.texture.unit[i].unitneeded && !(dwords <= atom->cmd_size))
dwords -= 4;
BEGIN_BATCH_NO_AUTOSTATE(dwords);
dwords -= 4;
BEGIN_BATCH_NO_AUTOSTATE(dwords);
@@
-718,7
+726,7
@@
static void tex_emit_mm(GLcontext *ctx, struct radeon_state_atom *atom)
}
}
-static void cube_emit(
GL
context *ctx, struct radeon_state_atom *atom)
+static void cube_emit(
struct gl_
context *ctx, struct radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
@@
-745,7
+753,7
@@
static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
END_BATCH();
}
END_BATCH();
}
-static void cube_emit_cs(
GL
context *ctx, struct radeon_state_atom *atom)
+static void cube_emit_cs(
struct gl_
context *ctx, struct radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
@@
-764,7
+772,7
@@
static void cube_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
for (j = 1; j <= 5; j++) {
OUT_BATCH(CP_PACKET0(R200_PP_CUBIC_OFFSET_F1_0 + (24*i) + (4 * (j-1)), 0));
OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
for (j = 1; j <= 5; j++) {
OUT_BATCH(CP_PACKET0(R200_PP_CUBIC_OFFSET_F1_0 + (24*i) + (4 * (j-1)), 0));
OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
- RADEON_GEM_DOMAIN_VRAM, 0, 0);
+ RADEON_GEM_DOMAIN_
GTT|RADEON_GEM_DOMAIN_
VRAM, 0, 0);
}
}
END_BATCH();
}
}
END_BATCH();
@@
-774,7
+782,7
@@
static void cube_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
*/
void r200InitState( r200ContextPtr rmesa )
{
*/
void r200InitState( r200ContextPtr rmesa )
{
-
GL
context *ctx = rmesa->radeon.glCtx;
+
struct gl_
context *ctx = rmesa->radeon.glCtx;
GLuint i;
rmesa->radeon.state.color.clear = 0x00000000;
GLuint i;
rmesa->radeon.state.color.clear = 0x00000000;
@@
-886,6
+894,11
@@
void r200InitState( r200ContextPtr rmesa )
}
}
}
}
+ if (rmesa->radeon.radeonScreen->kernel_mm)
+ ALLOC_STATE( stp, polygon_stipple, STP_STATE_SIZE, "STP/stp", 0 );
+ else
+ ALLOC_STATE( stp, never, STP_STATE_SIZE, "STP/stp", 0 );
+
for (i = 0; i < 6; i++)
if (rmesa->radeon.radeonScreen->kernel_mm)
rmesa->hw.tex[i].emit = tex_emit_mm;
for (i = 0; i < 6; i++)
if (rmesa->radeon.radeonScreen->kernel_mm)
rmesa->hw.tex[i].emit = tex_emit_mm;
@@
-1116,6
+1129,10
@@
void r200InitState( r200ContextPtr rmesa )
rmesa->hw.sci.cmd[SCI_CMD_1] = CP_PACKET0(R200_RE_TOP_LEFT, 0);
rmesa->hw.sci.cmd[SCI_CMD_2] = CP_PACKET0(R200_RE_WIDTH_HEIGHT, 0);
rmesa->hw.sci.cmd[SCI_CMD_1] = CP_PACKET0(R200_RE_TOP_LEFT, 0);
rmesa->hw.sci.cmd[SCI_CMD_2] = CP_PACKET0(R200_RE_WIDTH_HEIGHT, 0);
+ rmesa->hw.stp.cmd[STP_CMD_0] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0);
+ rmesa->hw.stp.cmd[STP_DATA_0] = 0;
+ rmesa->hw.stp.cmd[STP_CMD_1] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31);
+
if (rmesa->radeon.radeonScreen->kernel_mm) {
rmesa->hw.mtl[0].emit = mtl_emit;
rmesa->hw.mtl[1].emit = mtl_emit;
if (rmesa->radeon.radeonScreen->kernel_mm) {
rmesa->hw.mtl[0].emit = mtl_emit;
rmesa->hw.mtl[1].emit = mtl_emit;
@@
-1372,7
+1389,7
@@
void r200InitState( r200ContextPtr rmesa )
rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
(/* R200_TEXCOORD_PROJ | */
rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
(/* R200_TEXCOORD_PROJ | */
-
0x100000
); /* Small default bias */
+
R200_LOD_BIAS_CORRECTION
); /* Small default bias */
if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];