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Merge branch 'mesa_7_6_branch'
[mesa.git]
/
src
/
mesa
/
drivers
/
dri
/
r600
/
r700_clear.c
diff --git
a/src/mesa/drivers/dri/r600/r700_clear.c
b/src/mesa/drivers/dri/r600/r700_clear.c
index b04441da28194ef5b072dc58c534e81c0179b062..c6546ab00c2e674daa81dd18e7949d33fc173103 100644
(file)
--- a/
src/mesa/drivers/dri/r600/r700_clear.c
+++ b/
src/mesa/drivers/dri/r600/r700_clear.c
@@
-31,11
+31,14
@@
#include "main/imports.h"
#include "main/mtypes.h"
#include "main/enums.h"
#include "main/imports.h"
#include "main/mtypes.h"
#include "main/enums.h"
+#include "swrast/swrast.h"
+#include "radeon_lock.h"
#include "r600_context.h"
#include "r700_shaderinst.h"
#include "r600_emit.h"
#include "r600_context.h"
#include "r700_shaderinst.h"
#include "r600_emit.h"
+#include "r700_clear.h"
static GLboolean r700ClearFast(context_t *context, GLbitfield mask)
{
static GLboolean r700ClearFast(context_t *context, GLbitfield mask)
{
@@
-43,17
+46,6
@@
static GLboolean r700ClearFast(context_t *context, GLbitfield mask)
return GL_FALSE;
}
return GL_FALSE;
}
-static void r700UserClear(GLcontext *ctx, GLuint mask)
-{
- radeon_clear_tris(ctx, mask);
-}
-
-#define R600_NEWPRIM( rmesa ) \
- do { \
- if ( rmesa->radeon.dma.flush ) \
- rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \
- } while (0)
-
void r700Clear(GLcontext * ctx, GLbitfield mask)
{
context_t *context = R700_CONTEXT(ctx);
void r700Clear(GLcontext * ctx, GLbitfield mask)
{
context_t *context = R700_CONTEXT(ctx);
@@
-63,24
+55,25
@@
void r700Clear(GLcontext * ctx, GLbitfield mask)
int i;
struct gl_framebuffer *fb = ctx->DrawBuffer;
int i;
struct gl_framebuffer *fb = ctx->DrawBuffer;
+ radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s %x\n", __func__, mask);
+
if( GL_TRUE == r700ClearFast(context, mask) )
{
return;
}
if( GL_TRUE == r700ClearFast(context, mask) )
{
return;
}
-
-#if 0
if (!context->radeon.radeonScreen->driScreen->dri2.enabled) {
LOCK_HARDWARE(&context->radeon);
UNLOCK_HARDWARE(&context->radeon);
if (dPriv->numClipRects == 0)
return;
}
if (!context->radeon.radeonScreen->driScreen->dri2.enabled) {
LOCK_HARDWARE(&context->radeon);
UNLOCK_HARDWARE(&context->radeon);
if (dPriv->numClipRects == 0)
return;
}
-#endif
R600_NEWPRIM(context);
if (colorMask == ~0)
tri_mask |= (mask & BUFFER_BITS_COLOR);
R600_NEWPRIM(context);
if (colorMask == ~0)
tri_mask |= (mask & BUFFER_BITS_COLOR);
+ else
+ tri_mask |= (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT));
/* HW stencil */
/* HW stencil */
@@
-110,11
+103,12
@@
void r700Clear(GLcontext * ctx, GLbitfield mask)
/* SW fallback clearing */
swrast_mask = mask & ~tri_mask;
/* SW fallback clearing */
swrast_mask = mask & ~tri_mask;
- if (tri_mask)
- r700UserClear(ctx, tri_mask);
+ if (tri_mask) {
+ radeonUserClear(ctx, tri_mask);
+ }
+
if (swrast_mask) {
if (swrast_mask) {
- if (RADEON_DEBUG & DEBUG_FALLBACKS)
- fprintf(stderr, "%s: swrast clear, mask: %x\n",
+ radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT, "%s: swrast clear, mask: %x\n",
__FUNCTION__, swrast_mask);
_swrast_Clear(ctx, swrast_mask);
}
__FUNCTION__, swrast_mask);
_swrast_Clear(ctx, swrast_mask);
}