-static void r700SetRenderTarget(context_t *context, int id)
-{
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
- struct radeon_renderbuffer *rrb;
- unsigned int nPitchInPixel;
-
- rrb = radeon_get_colorbuffer(&context->radeon);
- if (!rrb || !rrb->bo) {
- fprintf(stderr, "no rrb\n");
- return;
- }
-
- /* screen/window/view */
- SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
-
- /* color buffer */
- r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
-
- nPitchInPixel = rrb->pitch/rrb->cpp;
- SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
- PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
- SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
- SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
- r700->render_target[id].CB_COLOR0_BASE.u32All = 0;
- SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
- SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
- CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
- if(4 == rrb->cpp)
- {
- SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
- CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
- SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
- }
- else
- {
- SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5,
- CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
- SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
- COMP_SWAP_shift, COMP_SWAP_mask);
- }
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
- SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
-
- r700->render_target[id].enabled = GL_TRUE;
-}
-
-static void r700SetDepthTarget(context_t *context)
-{
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
- struct radeon_renderbuffer *rrb;
- unsigned int nPitchInPixel;
-
- rrb = radeon_get_depthbuffer(&context->radeon);
- if (!rrb)
- return;
-
- /* depth buf */
- r700->DB_DEPTH_SIZE.u32All = 0;
- r700->DB_DEPTH_BASE.u32All = 0;
- r700->DB_DEPTH_INFO.u32All = 0;
- r700->DB_DEPTH_VIEW.u32All = 0;
-
- nPitchInPixel = rrb->pitch/rrb->cpp;
-
- SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
- PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
- SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
- SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
-
- if(4 == rrb->cpp)
- {
- switch (GL_CONTEXT(context)->Visual.depthBits)
- {
- case 16:
- case 24:
- SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
- DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
- break;
- default:
- fprintf(stderr, "Error: Unsupported depth %d... exiting\n",
- GL_CONTEXT(context)->Visual.depthBits);
- _mesa_exit(-1);
- }
- }
- else
- {
- SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
- DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
- }
- SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
- DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
- /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
-}
-