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Merge remote branch 'origin/master' into gallium_draw_llvm
[mesa.git]
/
src
/
mesa
/
drivers
/
dri
/
radeon
/
radeon_ioctl.c
diff --git
a/src/mesa/drivers/dri/radeon/radeon_ioctl.c
b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
index 1bda9cbe09c666cb73933a70a2129c30d82cd862..5ac526c6debaae4b131b738949b7a34266e5211a 100644
(file)
--- a/
src/mesa/drivers/dri/radeon/radeon_ioctl.c
+++ b/
src/mesa/drivers/dri/radeon/radeon_ioctl.c
@@
-38,18
+38,8
@@
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include <errno.h>
#include "main/attrib.h"
#include <errno.h>
#include "main/attrib.h"
-#include "main/enable.h"
-#include "main/blend.h"
#include "main/bufferobj.h"
#include "main/bufferobj.h"
-#include "main/buffers.h"
-#include "main/depth.h"
-#include "main/shaders.h"
-#include "main/texstate.h"
-#include "main/varray.h"
-#include "glapi/dispatch.h"
#include "swrast/swrast.h"
#include "swrast/swrast.h"
-#include "main/stencil.h"
-#include "main/matrix.h"
#include "main/glheader.h"
#include "main/imports.h"
#include "main/glheader.h"
#include "main/imports.h"
@@
-58,15
+48,10
@@
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "radeon_context.h"
#include "radeon_common.h"
#include "radeon_context.h"
#include "radeon_common.h"
-#include "radeon_state.h"
#include "radeon_ioctl.h"
#include "radeon_ioctl.h"
-#include "radeon_tcl.h"
-#include "radeon_sanity.h"
#define STANDALONE_MMIO
#define STANDALONE_MMIO
-#include "radeon_macros.h" /* for INREG() */
-#include "drirenderbuffer.h"
#include "vblank.h"
#define RADEON_TIMEOUT 512
#include "vblank.h"
#define RADEON_TIMEOUT 512
@@
-107,6
+92,8
@@
void radeonSetUpAtomList( r100ContextPtr rmesa )
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.lit[i]);
for (i = 0; i < 6; ++i)
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.ucp[i]);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.lit[i]);
for (i = 0; i < 6; ++i)
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.ucp[i]);
+ if (rmesa->radeon.radeonScreen->kernel_mm)
+ insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.stp);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.eye);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.grd);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.fog);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.eye);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.grd);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.fog);
@@
-127,8
+114,8
@@
static void radeonEmitScissor(r100ContextPtr rmesa)
OUT_BATCH((rmesa->radeon.state.scissor.rect.y1 << 16) |
rmesa->radeon.state.scissor.rect.x1);
OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
OUT_BATCH((rmesa->radeon.state.scissor.rect.y1 << 16) |
rmesa->radeon.state.scissor.rect.x1);
OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
- OUT_BATCH(((rmesa->radeon.state.scissor.rect.y2
- 1
) << 16) |
- (rmesa->radeon.state.scissor.rect.x2
- 1
));
+ OUT_BATCH(((rmesa->radeon.state.scissor.rect.y2) << 16) |
+ (rmesa->radeon.state.scissor.rect.x2));
END_BATCH();
} else {
BEGIN_BATCH(2);
END_BATCH();
} else {
BEGIN_BATCH(2);
@@
-200,7
+187,7
@@
void radeonFlushElts( GLcontext *ctx )
uint32_t *cmd = (uint32_t *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_start);
int dwords = (rmesa->radeon.cmdbuf.cs->section_ndw - rmesa->radeon.cmdbuf.cs->section_cdw);
uint32_t *cmd = (uint32_t *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_start);
int dwords = (rmesa->radeon.cmdbuf.cs->section_ndw - rmesa->radeon.cmdbuf.cs->section_cdw);
- if (RADEON_DEBUG &
DEBUG
_IOCTL)
+ if (RADEON_DEBUG &
RADEON
_IOCTL)
fprintf(stderr, "%s\n", __FUNCTION__);
assert( rmesa->radeon.dma.flush == radeonFlushElts );
fprintf(stderr, "%s\n", __FUNCTION__);
assert( rmesa->radeon.dma.flush == radeonFlushElts );
@@
-236,7
+223,7
@@
void radeonFlushElts( GLcontext *ctx )
END_BATCH();
END_BATCH();
- if (RADEON_DEBUG &
DEBUG
_SYNC) {
+ if (RADEON_DEBUG &
RADEON
_SYNC) {
fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
radeonFinish( rmesa->radeon.glCtx );
}
fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
radeonFinish( rmesa->radeon.glCtx );
}
@@
-252,7
+239,7
@@
GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa,
int align_min_nr;
BATCH_LOCALS(&rmesa->radeon);
int align_min_nr;
BATCH_LOCALS(&rmesa->radeon);
- if (RADEON_DEBUG &
DEBUG
_IOCTL)
+ if (RADEON_DEBUG &
RADEON
_IOCTL)
fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive);
assert((primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive);
assert((primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
@@
-296,7
+283,7
@@
GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa,
retval = (GLushort *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_offset);
retval = (GLushort *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_offset);
- if (RADEON_DEBUG &
DEBUG_PRIMS
)
+ if (RADEON_DEBUG &
RADEON_RENDER
)
fprintf(stderr, "%s: header prim %x \n",
__FUNCTION__, primitive);
fprintf(stderr, "%s: header prim %x \n",
__FUNCTION__, primitive);
@@
-318,7
+305,7
@@
void radeonEmitVertexAOS( r100ContextPtr rmesa,
#else
BATCH_LOCALS(&rmesa->radeon);
#else
BATCH_LOCALS(&rmesa->radeon);
- if (RADEON_DEBUG & (
DEBUG
_PRIMS|DEBUG_IOCTL))
+ if (RADEON_DEBUG & (
RADEON
_PRIMS|DEBUG_IOCTL))
fprintf(stderr, "%s: vertex_size 0x%x offset 0x%x \n",
__FUNCTION__, vertex_size, offset);
fprintf(stderr, "%s: vertex_size 0x%x offset 0x%x \n",
__FUNCTION__, vertex_size, offset);
@@
-350,7
+337,7
@@
void radeonEmitAOS( r100ContextPtr rmesa,
int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2;
int i;
int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2;
int i;
- if (RADEON_DEBUG &
DEBUG
_IOCTL)
+ if (RADEON_DEBUG &
RADEON
_IOCTL)
fprintf(stderr, "%s\n", __FUNCTION__);
BEGIN_BATCH(sz+2+(nr * 2));
fprintf(stderr, "%s\n", __FUNCTION__);
BEGIN_BATCH(sz+2+(nr * 2));
@@
-449,12
+436,14
@@
void radeonEmitAOS( r100ContextPtr rmesa,
static void radeonKernelClear(GLcontext *ctx, GLuint flags)
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
static void radeonKernelClear(GLcontext *ctx, GLuint flags)
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
- __DRIdrawable
Private
*dPriv = radeon_get_drawable(&rmesa->radeon);
+ __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon);
drm_radeon_sarea_t *sarea = rmesa->radeon.sarea;
uint32_t clear;
GLint ret, i;
GLint cx, cy, cw, ch;
drm_radeon_sarea_t *sarea = rmesa->radeon.sarea;
uint32_t clear;
GLint ret, i;
GLint cx, cy, cw, ch;
+ radeonEmitState(&rmesa->radeon);
+
LOCK_HARDWARE( &rmesa->radeon );
/* compute region after locking: */
LOCK_HARDWARE( &rmesa->radeon );
/* compute region after locking: */
@@
-570,12
+559,16
@@
static void radeonKernelClear(GLcontext *ctx, GLuint flags)
static void radeonClear( GLcontext *ctx, GLbitfield mask )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
static void radeonClear( GLcontext *ctx, GLbitfield mask )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
- __DRIdrawable
Private
*dPriv = radeon_get_drawable(&rmesa->radeon);
+ __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon);
GLuint flags = 0;
GLuint color_mask = 0;
GLuint orig_mask = mask;
GLuint flags = 0;
GLuint color_mask = 0;
GLuint orig_mask = mask;
- if ( RADEON_DEBUG & DEBUG_IOCTL ) {
+ if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) {
+ rmesa->radeon.front_buffer_dirty = GL_TRUE;
+ }
+
+ if ( RADEON_DEBUG & RADEON_IOCTL ) {
fprintf( stderr, "radeonClear\n");
}
fprintf( stderr, "radeonClear\n");
}
@@
-611,7
+604,7
@@
static void radeonClear( GLcontext *ctx, GLbitfield mask )
}
if ( mask ) {
}
if ( mask ) {
- if (RADEON_DEBUG &
DEBUG
_FALLBACKS)
+ if (RADEON_DEBUG &
RADEON
_FALLBACKS)
fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask);
_swrast_Clear( ctx, mask );
}
fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask);
_swrast_Clear( ctx, mask );
}