-static void calculate_miptree_layout_r300(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
-{
- GLuint curOffset, i, level;
-
- assert(mt->numLevels <= rmesa->glCtx->Const.MaxTextureLevels);
-
- curOffset = 0;
- for(i = 0, level = mt->baseLevel; i < mt->numLevels; i++, level++) {
- GLuint face;
-
- mt->levels[level].valid = 1;
- mt->levels[level].width = minify(mt->width0, i);
- mt->levels[level].height = minify(mt->height0, i);
- mt->levels[level].depth = minify(mt->depth0, i);
-
- for(face = 0; face < mt->faces; face++)
- compute_tex_image_offset(rmesa, mt, face, level, &curOffset);
- /* r600 cube levels seems to be aligned to 8 faces but
- * we have separate register for 1'st level offset so add
- * 2 image alignment after 1'st mip level */
- if(rmesa->radeonScreen->chip_family >= CHIP_FAMILY_R600 &&
- mt->target == GL_TEXTURE_CUBE_MAP && level >= 1)
- curOffset += 2 * mt->levels[level].size;
- }
-
- /* Note the required size in memory */
- mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK;
-
- radeon_print(RADEON_TEXTURE, RADEON_TRACE,
- "%s(%p, %p) total size %d\n",
- __func__, rmesa, mt, mt->totalsize);
-}
-