- radeon_teximage_map(baseimage, GL_FALSE);
- radeon_generate_mipmap(ctx, target, texObj);
- radeon_teximage_unmap(baseimage);
+ if (_mesa_meta_check_generate_mipmap_fallback(ctx, target, texObj)) {
+ radeon_teximage_map(baseimage, GL_FALSE);
+ radeon_generate_mipmap(ctx, target, texObj);
+ radeon_teximage_unmap(baseimage);
+ } else {
+ _mesa_meta_GenerateMipmap(ctx, target, texObj);
+ }
+ case GL_COMPRESSED_SRGB_S3TC_DXT1_EXT:
+ return MESA_FORMAT_SRGB_DXT1;
+ case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT1_EXT:
+ return MESA_FORMAT_SRGBA_DXT1;
+ case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT3_EXT:
+ return MESA_FORMAT_SRGBA_DXT3;
+ case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT5_EXT:
+ return MESA_FORMAT_SRGBA_DXT5;
+
radeon_texsubimage(ctx, 3, target, level, xoffset, yoffset, zoffset, width, height, depth, 0,
format, type, pixels, packing, texObj, texImage, 0);
}
radeon_texsubimage(ctx, 3, target, level, xoffset, yoffset, zoffset, width, height, depth, 0,
format, type, pixels, packing, texObj, texImage, 0);
}
+
+unsigned radeonIsFormatRenderable(gl_format mesa_format)
+{
+ if (mesa_format == _dri_texformat_argb8888 || mesa_format == _dri_texformat_rgb565 ||
+ mesa_format == _dri_texformat_argb1555 || mesa_format == _dri_texformat_argb4444)
+ return 1;
+
+ switch (mesa_format)
+ {
+ case MESA_FORMAT_Z16:
+ case MESA_FORMAT_S8_Z24:
+ return 1;
+ default:
+ return 0;
+ }
+}