+}
+
+static int RADEONColorTilingInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
+{
+ int width_bytes = ctx->shared.virtualWidth * ctx->cpp;
+ int bufferSize = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes + RADEON_BUFFER_ALIGN)
+ & ~RADEON_BUFFER_ALIGN);
+ /* Setup color tiling */
+ if (info->drmMinor<14)
+ info->colorTiling=0;
+
+ if (info->colorTiling)
+ {
+
+ int colorTilingFlag;
+ drm_radeon_surface_alloc_t front,back;
+
+ RadeonSetParam(ctx, RADEON_SETPARAM_SWITCH_TILING, info->colorTiling ? 1 : 0);
+
+ /* Setup the surfaces */
+ if (info->ChipFamily < CHIP_FAMILY_R200)
+ colorTilingFlag=RADEON_SURF_TILE_COLOR_MACRO;
+ else
+ colorTilingFlag=R200_SURF_TILE_COLOR_MACRO;
+
+ front.address = info->frontOffset;
+ front.size = bufferSize;
+ front.flags = (width_bytes) | colorTilingFlag;
+ drmCommandWrite(ctx->drmFD, DRM_RADEON_SURF_ALLOC, &front,sizeof(front));
+
+ back.address = info->backOffset;
+ back.size = bufferSize;
+ back.flags = (width_bytes) | colorTilingFlag;
+ drmCommandWrite(ctx->drmFD, DRM_RADEON_SURF_ALLOC, &back,sizeof(back));
+
+ }
+ return 1;