+
+ /* Important:
+ */
+ VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
+ smesa->vertex_attr_count = 0;
+
+ /* EMIT_ATTR's must be in order as they tell t_vertex.c how to build up a
+ * hardware vertex.
+ */
+
+ AGPParseSet &= ~(MASK_VertexDWSize | MASK_VertexDataFormat);
+ AGPParseSet |= SiS_PS_HAS_XYZ | SiS_PS_HAS_DIFFUSE;
+ if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) {
+ EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_4F_VIEWPORT);
+ AGPParseSet |= SiS_PS_HAS_W;
+ smesa->coloroffset = 4;
+ } else {
+ EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_3F_VIEWPORT);
+ smesa->coloroffset = 3;
+ }
+
+ EMIT_ATTR(_TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA);
+
+ smesa->specoffset = 0;
+ if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 ) ||
+ RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
+ AGPParseSet |= SiS_PS_HAS_SPECULAR;
+
+ if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
+ EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR);
+ smesa->specoffset = smesa->coloroffset + 1;
+ } else {
+ EMIT_PAD(3);
+ }
+
+ if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
+ EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1UB_1F);
+ } else {
+ EMIT_PAD(1);
+ }
+ }
+
+ /* projective textures are not supported by the hardware */
+ if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX0 )) {
+ if (VB->TexCoordPtr[0]->size > 2)
+ tex_fallback = GL_TRUE;
+ EMIT_ATTR(_TNL_ATTRIB_TEX0, EMIT_2F);
+ AGPParseSet |= SiS_PS_HAS_UV0;
+ }
+ /* Will only hit tex1 on SiS300 */
+ if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX1 )) {
+ if (VB->TexCoordPtr[1]->size > 2)
+ tex_fallback = GL_TRUE;
+ EMIT_ATTR(_TNL_ATTRIB_TEX1, EMIT_2F);
+ AGPParseSet |= SiS_PS_HAS_UV1;
+ }
+ FALLBACK(smesa, SIS_FALLBACK_TEXTURE, tex_fallback);
+
+ if (!RENDERINPUTS_EQUAL( smesa->last_tcl_state_bitset, index_bitset )) {
+ smesa->AGPParseSet = AGPParseSet;
+
+ smesa->vertex_size = _tnl_install_attrs( ctx, smesa->vertex_attrs,
+ smesa->vertex_attr_count, smesa->hw_viewport, 0 );
+
+ smesa->vertex_size >>= 2;
+ smesa->AGPParseSet |= smesa->vertex_size << 28;
+ }