- .alu = {
- .op = midgard_alu_op_imov,
- .reg_mode = midgard_reg_mode_32,
- .dest_override = midgard_dest_override_none,
- .outmod = midgard_outmod_int_wrap,
- .src1 = vector_alu_srco_unsigned(zero_alu_src),
- .src2 = vector_alu_srco_unsigned(mod)
+ .dest_type = nir_type_uint32,
+ .op = midgard_alu_op_imov,
+ .outmod = midgard_outmod_int_wrap
+ };
+
+ return ins;
+}
+
+/* Broad types of register classes so we can handle special
+ * registers */
+
+#define REG_CLASS_WORK 0
+#define REG_CLASS_LDST 1
+#define REG_CLASS_TEXR 3
+#define REG_CLASS_TEXW 4
+
+/* Like a move, but to thread local storage! */
+
+static inline midgard_instruction
+v_load_store_scratch(
+ unsigned srcdest,
+ unsigned index,
+ bool is_store,
+ unsigned mask)
+{
+ /* We index by 32-bit vec4s */
+ unsigned byte = (index * 4 * 4);
+
+ midgard_instruction ins = {
+ .type = TAG_LOAD_STORE_4,
+ .mask = mask,
+ .dest_type = nir_type_uint32,
+ .dest = ~0,
+ .src = { ~0, ~0, ~0, ~0 },
+ .swizzle = SWIZZLE_IDENTITY_4,
+ .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
+ .load_store = {
+ /* For register spilling - to thread local storage */
+ .arg_1 = 0xEA,
+ .arg_2 = 0x1E,