+/* 64-bit swizzles are super easy since there are 2 components of 2 components
+ * in an 8-bit field ... lots of duplication to go around!
+ *
+ * Swizzles of 32-bit vectors accessed from 64-bit instructions are a little
+ * funny -- pack them *as if* they were native 64-bit, using rep_* flags to
+ * flag upper. For instance, xy would become 64-bit XY but that's just xyzw
+ * native. Likewise, zz would become 64-bit XX with rep* so it would be xyxy
+ * with rep. Pretty nifty, huh? */
+
+static unsigned
+mir_pack_swizzle_64(unsigned *swizzle, unsigned max_component)
+{
+ unsigned packed = 0;
+
+ for (unsigned i = 0; i < 2; ++i) {
+ assert(swizzle[i] <= max_component);
+
+ unsigned a = (swizzle[i] & 1) ?
+ (COMPONENT_W << 2) | COMPONENT_Z :
+ (COMPONENT_Y << 2) | COMPONENT_X;
+
+ packed |= a << (i * 4);
+ }
+
+ return packed;
+}
+
+static void
+mir_pack_mask_alu(midgard_instruction *ins, midgard_vector_alu *alu)
+{
+ unsigned effective = ins->mask;
+
+ /* If we have a destination override, we need to figure out whether to
+ * override to the lower or upper half, shifting the effective mask in
+ * the latter, so AAAA.... becomes AAAA */
+
+ unsigned inst_size = max_bitsize_for_alu(ins);
+ signed upper_shift = mir_upper_override(ins, inst_size);
+
+ if (upper_shift >= 0) {
+ effective >>= upper_shift;
+ alu->dest_override = upper_shift ?
+ midgard_dest_override_upper :
+ midgard_dest_override_lower;
+ } else {
+ alu->dest_override = midgard_dest_override_none;
+ }
+
+ if (inst_size == 32)
+ alu->mask = expand_writemask(effective, 2);
+ else if (inst_size == 64)
+ alu->mask = expand_writemask(effective, 1);
+ else
+ alu->mask = effective;
+}
+
+static unsigned
+mir_pack_swizzle(unsigned mask, unsigned *swizzle,
+ nir_alu_type T, midgard_reg_mode reg_mode,
+ bool op_channeled, bool *rep_low, bool *rep_high)
+{
+ unsigned packed = 0;
+ unsigned sz = nir_alu_type_get_type_size(T);
+
+ if (reg_mode == midgard_reg_mode_64) {
+ assert(sz == 64 || sz == 32);
+ unsigned components = (sz == 32) ? 4 : 2;
+
+ packed = mir_pack_swizzle_64(swizzle, components);
+
+ if (sz == 32) {
+ bool lo = swizzle[0] >= COMPONENT_Z;
+ bool hi = swizzle[1] >= COMPONENT_Z;
+
+ if (mask & 0x1) {
+ /* We can't mix halves... */
+ if (mask & 2)
+ assert(lo == hi);
+
+ *rep_low = lo;
+ } else {
+ *rep_low = hi;
+ }
+ } else if (sz < 32) {
+ unreachable("Cannot encode 8/16 swizzle in 64-bit");
+ }
+ } else {
+ /* For 32-bit, swizzle packing is stupid-simple. For 16-bit,
+ * the strategy is to check whether the nibble we're on is
+ * upper or lower. We need all components to be on the same
+ * "side"; that much is enforced by the ISA and should have
+ * been lowered. TODO: 8-bit packing. TODO: vec8 */
+
+ unsigned first = mask ? ffs(mask) - 1 : 0;
+ bool upper = swizzle[first] > 3;
+
+ if (upper && mask)
+ assert(sz <= 16);
+
+ bool dest_up = !op_channeled && (first >= 4);
+
+ for (unsigned c = (dest_up ? 4 : 0); c < (dest_up ? 8 : 4); ++c) {
+ unsigned v = swizzle[c];
+
+ bool t_upper = v > 3;
+
+ /* Ensure we're doing something sane */
+
+ if (mask & (1 << c)) {
+ assert(t_upper == upper);
+ assert(v <= 7);
+ }
+
+ /* Use the non upper part */
+ v &= 0x3;
+
+ packed |= v << (2 * (c % 4));
+ }
+
+
+ /* Replicate for now.. should really pick a side for
+ * dot products */
+
+ if (reg_mode == midgard_reg_mode_16 && sz == 16) {
+ *rep_low = !upper;
+ *rep_high = upper;
+ } else if (reg_mode == midgard_reg_mode_16 && sz == 8) {
+ *rep_low = upper;
+ *rep_high = upper;
+ } else if (reg_mode == midgard_reg_mode_32) {
+ *rep_low = upper;
+ } else {
+ unreachable("Unhandled reg mode");
+ }
+ }
+
+ return packed;
+}
+
+static void
+mir_pack_vector_srcs(midgard_instruction *ins, midgard_vector_alu *alu)
+{
+ bool channeled = GET_CHANNEL_COUNT(alu_opcode_props[ins->op].props);
+
+ unsigned base_size = max_bitsize_for_alu(ins);
+
+ for (unsigned i = 0; i < 2; ++i) {
+ if (ins->has_inline_constant && (i == 1))
+ continue;
+
+ if (ins->src[i] == ~0)
+ continue;
+
+ bool rep_lo = false, rep_hi = false;
+ unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]);
+ bool half = (sz == (base_size >> 1));
+
+ assert((sz == base_size) || half);
+
+ unsigned swizzle = mir_pack_swizzle(ins->mask, ins->swizzle[i],
+ ins->src_types[i], reg_mode_for_bitsize(base_size),
+ channeled, &rep_lo, &rep_hi);
+
+ midgard_vector_alu_src pack = {
+ .mod = mir_pack_mod(ins, i, false),
+ .rep_low = rep_lo,
+ .rep_high = rep_hi,
+ .half = half,
+ .swizzle = swizzle
+ };
+
+ unsigned p = vector_alu_srco_unsigned(pack);
+
+ if (i == 0)
+ alu->src1 = p;
+ else
+ alu->src2 = p;
+ }
+}
+
+static void
+mir_pack_swizzle_ldst(midgard_instruction *ins)
+{
+ /* TODO: non-32-bit, non-vec4 */
+ for (unsigned c = 0; c < 4; ++c) {
+ unsigned v = ins->swizzle[0][c];
+
+ /* Check vec4 */
+ assert(v <= 3);
+
+ ins->load_store.swizzle |= v << (2 * c);
+ }
+
+ /* TODO: arg_1/2 */
+}
+
+static void
+mir_pack_swizzle_tex(midgard_instruction *ins)
+{
+ for (unsigned i = 0; i < 2; ++i) {
+ unsigned packed = 0;
+
+ for (unsigned c = 0; c < 4; ++c) {
+ unsigned v = ins->swizzle[i][c];
+
+ /* Check vec4 */
+ assert(v <= 3);
+
+ packed |= v << (2 * c);
+ }
+
+ if (i == 0)
+ ins->texture.swizzle = packed;
+ else
+ ins->texture.in_reg_swizzle = packed;
+ }
+
+ /* TODO: bias component */
+}
+
+/* Up to 3 { ALU, LDST } bundles can execute in parallel with a texture op.
+ * Given a texture op, lookahead to see how many such bundles we can flag for
+ * OoO execution */
+
+static bool
+mir_can_run_ooo(midgard_block *block, midgard_bundle *bundle,
+ unsigned dependency)
+{
+ /* Don't read out of bounds */
+ if (bundle >= (midgard_bundle *) ((char *) block->bundles.data + block->bundles.size))
+ return false;
+
+ /* Texture ops can't execute with other texture ops */
+ if (!IS_ALU(bundle->tag) && bundle->tag != TAG_LOAD_STORE_4)
+ return false;
+
+ /* Ensure there is no read-after-write dependency */
+
+ for (unsigned i = 0; i < bundle->instruction_count; ++i) {
+ midgard_instruction *ins = bundle->instructions[i];
+
+ mir_foreach_src(ins, s) {
+ if (ins->src[s] == dependency)
+ return false;
+ }
+ }
+
+ /* Otherwise, we're okay */
+ return true;
+}
+
+static void
+mir_pack_tex_ooo(midgard_block *block, midgard_bundle *bundle, midgard_instruction *ins)
+{
+ unsigned count = 0;
+
+ for (count = 0; count < 3; ++count) {
+ if (!mir_can_run_ooo(block, bundle + count + 1, ins->dest))
+ break;
+ }
+
+ ins->texture.out_of_order = count;
+}
+
+/* Load store masks are 4-bits. Load/store ops pack for that. vec4 is the
+ * natural mask width; vec8 is constrained to be in pairs, vec2 is duplicated. TODO: 8-bit?
+ */
+
+static void
+mir_pack_ldst_mask(midgard_instruction *ins)
+{
+ unsigned sz = nir_alu_type_get_type_size(ins->dest_type);
+ unsigned packed = ins->mask;
+
+ if (sz == 64) {
+ packed = ((ins->mask & 0x2) ? (0x8 | 0x4) : 0) |
+ ((ins->mask & 0x1) ? (0x2 | 0x1) : 0);
+ } else if (sz == 16) {
+ packed = 0;
+
+ for (unsigned i = 0; i < 4; ++i) {
+ /* Make sure we're duplicated */
+ bool u = (ins->mask & (1 << (2*i + 0))) != 0;
+ bool v = (ins->mask & (1 << (2*i + 1))) != 0;
+ assert(u == v);
+
+ packed |= (u << i);
+ }
+ } else {
+ assert(sz == 32);
+ }
+
+ ins->load_store.mask = packed;
+}
+
+static void
+mir_lower_inverts(midgard_instruction *ins)
+{
+ bool inv[3] = {
+ ins->src_invert[0],
+ ins->src_invert[1],
+ ins->src_invert[2]
+ };
+
+ switch (ins->op) {
+ case midgard_alu_op_iand:
+ /* a & ~b = iandnot(a, b) */
+ /* ~a & ~b = ~(a | b) = inor(a, b) */
+
+ if (inv[0] && inv[1])
+ ins->op = midgard_alu_op_inor;
+ else if (inv[1])
+ ins->op = midgard_alu_op_iandnot;
+
+ break;
+ case midgard_alu_op_ior:
+ /* a | ~b = iornot(a, b) */
+ /* ~a | ~b = ~(a & b) = inand(a, b) */
+
+ if (inv[0] && inv[1])
+ ins->op = midgard_alu_op_inand;
+ else if (inv[1])
+ ins->op = midgard_alu_op_iornot;
+
+ break;
+
+ case midgard_alu_op_ixor:
+ /* ~a ^ b = a ^ ~b = ~(a ^ b) = inxor(a, b) */
+ /* ~a ^ ~b = a ^ b */
+
+ if (inv[0] ^ inv[1])
+ ins->op = midgard_alu_op_inxor;
+
+ break;
+
+ default:
+ break;
+ }
+}
+
+/* Opcodes with ROUNDS are the base (rte/0) type so we can just add */
+
+static void
+mir_lower_roundmode(midgard_instruction *ins)
+{
+ if (alu_opcode_props[ins->op].props & MIDGARD_ROUNDS) {
+ assert(ins->roundmode <= 0x3);
+ ins->op += ins->roundmode;
+ }
+}
+
+static midgard_load_store_word
+load_store_from_instr(midgard_instruction *ins)
+{
+ midgard_load_store_word ldst = ins->load_store;
+ ldst.op = ins->op;
+
+ if (OP_IS_STORE(ldst.op)) {
+ ldst.reg = SSA_REG_FROM_FIXED(ins->src[0]) & 1;
+ } else {
+ ldst.reg = SSA_REG_FROM_FIXED(ins->dest);
+ }
+
+ if (ins->src[1] != ~0) {
+ unsigned src = SSA_REG_FROM_FIXED(ins->src[1]);
+ unsigned sz = nir_alu_type_get_type_size(ins->src_types[1]);
+ ldst.arg_1 |= midgard_ldst_reg(src, ins->swizzle[1][0], sz);
+ }
+
+ if (ins->src[2] != ~0) {
+ unsigned src = SSA_REG_FROM_FIXED(ins->src[2]);
+ unsigned sz = nir_alu_type_get_type_size(ins->src_types[2]);
+ ldst.arg_2 |= midgard_ldst_reg(src, ins->swizzle[2][0], sz);
+ }
+
+ return ldst;
+}
+
+static midgard_texture_word
+texture_word_from_instr(midgard_instruction *ins)
+{
+ midgard_texture_word tex = ins->texture;
+ tex.op = ins->op;
+
+ unsigned src1 = ins->src[1] == ~0 ? REGISTER_UNUSED : SSA_REG_FROM_FIXED(ins->src[1]);
+ tex.in_reg_select = src1 & 1;
+
+ unsigned dest = ins->dest == ~0 ? REGISTER_UNUSED : SSA_REG_FROM_FIXED(ins->dest);
+ tex.out_reg_select = dest & 1;
+
+ if (ins->src[2] != ~0) {
+ midgard_tex_register_select sel = {
+ .select = SSA_REG_FROM_FIXED(ins->src[2]) & 1,
+ .full = 1,
+ .component = ins->swizzle[2][0]
+ };
+ uint8_t packed;
+ memcpy(&packed, &sel, sizeof(packed));
+ tex.bias = packed;
+ }
+
+ if (ins->src[3] != ~0) {
+ unsigned x = ins->swizzle[3][0];
+ unsigned y = x + 1;
+ unsigned z = x + 2;
+
+ /* Check range, TODO: half-registers */
+ assert(z < 4);
+
+ unsigned offset_reg = SSA_REG_FROM_FIXED(ins->src[3]);
+ tex.offset =
+ (1) | /* full */
+ (offset_reg & 1) << 1 | /* select */
+ (0 << 2) | /* upper */
+ (x << 3) | /* swizzle */
+ (y << 5) | /* swizzle */
+ (z << 7); /* swizzle */
+ }
+
+ return tex;
+}
+
+static midgard_vector_alu
+vector_alu_from_instr(midgard_instruction *ins)
+{
+ midgard_vector_alu alu = {
+ .op = ins->op,
+ .outmod = ins->outmod,
+ .reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins))
+ };
+
+ if (ins->has_inline_constant) {
+ /* Encode inline 16-bit constant. See disassembler for
+ * where the algorithm is from */
+
+ int lower_11 = ins->inline_constant & ((1 << 12) - 1);
+ uint16_t imm = ((lower_11 >> 8) & 0x7) |
+ ((lower_11 & 0xFF) << 3);
+
+ alu.src2 = imm << 2;
+ }
+
+ return alu;
+}
+
+static midgard_branch_extended
+midgard_create_branch_extended( midgard_condition cond,
+ midgard_jmp_writeout_op op,
+ unsigned dest_tag,
+ signed quadword_offset)
+{
+ /* The condition code is actually a LUT describing a function to
+ * combine multiple condition codes. However, we only support a single
+ * condition code at the moment, so we just duplicate over a bunch of
+ * times. */
+
+ uint16_t duplicated_cond =
+ (cond << 14) |
+ (cond << 12) |
+ (cond << 10) |
+ (cond << 8) |
+ (cond << 6) |
+ (cond << 4) |
+ (cond << 2) |
+ (cond << 0);
+
+ midgard_branch_extended branch = {
+ .op = op,
+ .dest_tag = dest_tag,
+ .offset = quadword_offset,
+ .cond = duplicated_cond
+ };
+
+ return branch;
+}
+
+static void
+emit_branch(midgard_instruction *ins,
+ compiler_context *ctx,
+ midgard_block *block,
+ midgard_bundle *bundle,
+ struct util_dynarray *emission)
+{
+ /* Parse some basic branch info */
+ bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
+ bool is_conditional = ins->branch.conditional;
+ bool is_inverted = ins->branch.invert_conditional;
+ bool is_discard = ins->branch.target_type == TARGET_DISCARD;
+ bool is_tilebuf_wait = ins->branch.target_type == TARGET_TILEBUF_WAIT;
+ bool is_special = is_discard || is_tilebuf_wait;
+ bool is_writeout = ins->writeout;
+
+ /* Determine the block we're jumping to */
+ int target_number = ins->branch.target_block;
+
+ /* Report the destination tag */
+ int dest_tag = is_discard ? 0 :
+ is_tilebuf_wait ? bundle->tag :
+ midgard_get_first_tag_from_block(ctx, target_number);
+
+ /* Count up the number of quadwords we're
+ * jumping over = number of quadwords until
+ * (br_block_idx, target_number) */
+
+ int quadword_offset = 0;
+
+ if (is_discard) {
+ /* Ignored */
+ } else if (is_tilebuf_wait) {
+ quadword_offset = -1;
+ } else if (target_number > block->base.name) {
+ /* Jump forward */
+
+ for (int idx = block->base.name+1; idx < target_number; ++idx) {
+ midgard_block *blk = mir_get_block(ctx, idx);
+ assert(blk);
+
+ quadword_offset += blk->quadword_count;
+ }
+ } else {
+ /* Jump backwards */
+
+ for (int idx = block->base.name; idx >= target_number; --idx) {
+ midgard_block *blk = mir_get_block(ctx, idx);
+ assert(blk);
+
+ quadword_offset -= blk->quadword_count;
+ }
+ }
+
+ /* Unconditional extended branches (far jumps)
+ * have issues, so we always use a conditional
+ * branch, setting the condition to always for
+ * unconditional. For compact unconditional
+ * branches, cond isn't used so it doesn't
+ * matter what we pick. */
+
+ midgard_condition cond =
+ !is_conditional ? midgard_condition_always :
+ is_inverted ? midgard_condition_false :
+ midgard_condition_true;
+
+ midgard_jmp_writeout_op op =
+ is_discard ? midgard_jmp_writeout_op_discard :
+ is_tilebuf_wait ? midgard_jmp_writeout_op_tilebuffer_pending :
+ is_writeout ? midgard_jmp_writeout_op_writeout :
+ (is_compact && !is_conditional) ?
+ midgard_jmp_writeout_op_branch_uncond :
+ midgard_jmp_writeout_op_branch_cond;
+
+ if (is_compact) {
+ unsigned size = sizeof(midgard_branch_cond);
+
+ if (is_conditional || is_special) {
+ midgard_branch_cond branch = {
+ .op = op,
+ .dest_tag = dest_tag,
+ .offset = quadword_offset,
+ .cond = cond
+ };
+ memcpy(util_dynarray_grow_bytes(emission, size, 1), &branch, size);
+ } else {
+ assert(op == midgard_jmp_writeout_op_branch_uncond);
+ midgard_branch_uncond branch = {
+ .op = op,
+ .dest_tag = dest_tag,
+ .offset = quadword_offset,
+ .unknown = 1
+ };
+ assert(branch.offset == quadword_offset);
+ memcpy(util_dynarray_grow_bytes(emission, size, 1), &branch, size);
+ }
+ } else { /* `ins->compact_branch`, misnomer */
+ unsigned size = sizeof(midgard_branch_extended);
+
+ midgard_branch_extended branch =
+ midgard_create_branch_extended(
+ cond, op,
+ dest_tag,
+ quadword_offset);
+
+ memcpy(util_dynarray_grow_bytes(emission, size, 1), &branch, size);
+ }
+}
+