+bool
+mir_nontrivial_source2_mod_simple(midgard_instruction *ins)
+{
+ bool is_int = midgard_is_integer_op(ins->alu.op);
+
+ midgard_vector_alu_src src2 =
+ vector_alu_from_unsigned(ins->alu.src2);
+
+ return mir_nontrivial_raw_mod(src2, is_int) || src2.half;
+}
+
+bool
+mir_nontrivial_outmod(midgard_instruction *ins)
+{
+ bool is_int = midgard_is_integer_op(ins->alu.op);
+ unsigned mod = ins->alu.outmod;
+
+ /* Pseudo-outmod */
+ if (ins->invert)
+ return true;
+
+ /* Type conversion is a sort of outmod */
+ if (ins->alu.dest_override != midgard_dest_override_none)
+ return true;
+
+ if (is_int)
+ return mod != midgard_outmod_int_wrap;
+ else
+ return mod != midgard_outmod_none;
+}
+
+/* Checks if an index will be used as a special register -- basically, if we're
+ * used as the input to a non-ALU op */
+
+bool
+mir_special_index(compiler_context *ctx, unsigned idx)
+{
+ mir_foreach_instr_global(ctx, ins) {
+ bool is_ldst = ins->type == TAG_LOAD_STORE_4;
+ bool is_tex = ins->type == TAG_TEXTURE_4;
+ bool is_writeout = ins->compact_branch && ins->writeout;
+
+ if (!(is_ldst || is_tex || is_writeout))
+ continue;
+
+ if (mir_has_arg(ins, idx))
+ return true;
+ }
+
+ return false;
+}
+
+/* Is a node written before a given instruction? */
+
+bool
+mir_is_written_before(compiler_context *ctx, midgard_instruction *ins, unsigned node)
+{
+ if (node >= SSA_FIXED_MINIMUM)
+ return true;
+
+ mir_foreach_instr_global(ctx, q) {
+ if (q == ins)
+ break;
+
+ if (q->dest == node)
+ return true;
+ }
+
+ return false;
+}
+
+/* Creates a mask of the components of a node read by an instruction, by
+ * analyzing the swizzle with respect to the instruction's mask. E.g.:
+ *
+ * fadd r0.xz, r1.yyyy, r2.zwyx
+ *
+ * will return a mask of Z/Y for r2
+ */
+
+static unsigned
+mir_mask_of_read_components_single(unsigned swizzle, unsigned outmask)
+{
+ unsigned mask = 0;
+
+ for (unsigned c = 0; c < 4; ++c) {
+ if (!(outmask & (1 << c))) continue;
+
+ unsigned comp = (swizzle >> (2*c)) & 3;
+ mask |= (1 << comp);
+ }
+
+ return mask;
+}
+
+static unsigned
+mir_source_count(midgard_instruction *ins)
+{
+ if (ins->type == TAG_ALU_4) {
+ /* ALU is always binary */
+ return 2;
+ } else if (ins->type == TAG_LOAD_STORE_4) {
+ bool load = !OP_IS_STORE(ins->load_store.op);
+ return (load ? 2 : 3);
+ } else if (ins->type == TAG_TEXTURE_4) {
+ /* Coords, bias.. TODO: Offsets? */
+ return 2;
+ } else {
+ unreachable("Invalid instruction type");
+ }
+}
+
+static unsigned
+mir_component_count_implicit(midgard_instruction *ins, unsigned i)
+{
+ if (ins->type == TAG_LOAD_STORE_4) {
+ switch (ins->load_store.op) {
+ /* Address implicitly 64-bit */
+ case midgard_op_ld_int4:
+ return (i == 0) ? 1 : 0;
+
+ case midgard_op_st_int4:
+ return (i == 1) ? 1 : 0;
+
+ default:
+ return 0;
+ }
+ }
+
+ return 0;
+}
+
+unsigned
+mir_mask_of_read_components(midgard_instruction *ins, unsigned node)
+{
+ unsigned mask = 0;
+
+ for (unsigned i = 0; i < mir_source_count(ins); ++i) {
+ if (ins->src[i] != node) continue;
+
+ unsigned swizzle = mir_get_swizzle(ins, i);
+ unsigned m = mir_mask_of_read_components_single(swizzle, ins->mask);
+
+ /* Sometimes multi-arg ops are passed implicitly */
+ unsigned implicit = mir_component_count_implicit(ins, i);
+ assert(implicit < 2);
+
+ /* Extend the mask */
+ if (implicit == 1) {
+ /* Ensure it's a single bit currently */
+ assert((m >> __builtin_ctz(m)) == 0x1);
+
+ /* Set the next bit to extend one*/
+ m |= (m << 1);
+ }
+
+ mask |= m;
+ }
+
+ return mask;
+}
+
+unsigned
+mir_ubo_shift(midgard_load_store_op op)
+{
+ switch (op) {
+ case midgard_op_ld_ubo_char:
+ return 0;
+ case midgard_op_ld_ubo_char2:
+ return 1;
+ case midgard_op_ld_ubo_char4:
+ return 2;
+ case midgard_op_ld_ubo_short4:
+ return 3;
+ case midgard_op_ld_ubo_int4:
+ return 4;
+ default:
+ unreachable("Invalid op");
+ }
+}
+
+/* Register allocation occurs after instruction scheduling, which is fine until
+ * we start needing to spill registers and therefore insert instructions into
+ * an already-scheduled program. We don't have to be terribly efficient about
+ * this, since spilling is already slow. So just semantically we need to insert
+ * the instruction into a new bundle before/after the bundle of the instruction
+ * in question */
+
+static midgard_bundle
+mir_bundle_for_op(compiler_context *ctx, midgard_instruction ins)
+{
+ midgard_instruction *u = mir_upload_ins(ctx, ins);
+
+ midgard_bundle bundle = {
+ .tag = ins.type,
+ .instruction_count = 1,
+ .instructions = { u },
+ };
+
+ if (bundle.tag == TAG_ALU_4) {
+ assert(OP_IS_MOVE(u->alu.op));
+ u->unit = UNIT_VMUL;
+
+ size_t bytes_emitted = sizeof(uint32_t) + sizeof(midgard_reg_info) + sizeof(midgard_vector_alu);
+ bundle.padding = ~(bytes_emitted - 1) & 0xF;
+ bundle.control = ins.type | u->unit;
+ }