+ print("UART Test PASSED!")
+
+
+def test_i2c(dut):
+ i2c_sda_i_pad = dut.jtag.boundary_scan_pads['i2c_0__sda__i']['i']
+ i2c_sda_o_pad = dut.jtag.boundary_scan_pads['i2c_0__sda__o']['o']
+ i2c_sda_oe_pad = dut.jtag.boundary_scan_pads['i2c_0__sda__oe']['o']
+
+ i2c_scl_i_pad = dut.jtag.boundary_scan_pads['i2c_0__scl__i']['i']
+ i2c_scl_o_pad = dut.jtag.boundary_scan_pads['i2c_0__scl__o']['o']
+ i2c_scl_oe_pad = dut.jtag.boundary_scan_pads['i2c_0__scl__oe']['o']
+
+ #i2c_pad = dut.jtag.resource_table_pads[('i2c', 0)]
+ #print ("i2c pad", i2c_pad)
+ #print ("i2c pad", i2c_pad.layout)
+
+ for i in range(0, 2):
+ yield i2c_sda_i_pad.eq(i) # i2c_pad.sda.i.eq(i)
+ yield i2c_scl_i_pad.eq(i) # i2c_pad.scl.i.eq(i)
+ yield dut.i2c_sda_oe_test.eq(i)
+ yield dut.i2c_scl_oe_test.eq(i)
+ yield Settle()
+ yield # one clock cycle
+ sda_o_val = yield i2c_sda_o_pad
+ scl_o_val = yield i2c_scl_o_pad
+ sda_oe_val = yield i2c_sda_oe_pad
+ scl_oe_val = yield i2c_scl_oe_pad
+ print("Test input: ", i, " SDA/SCL out: ", sda_o_val, scl_o_val,
+ " SDA/SCL oe: ", sda_oe_val, scl_oe_val)
+ assert sda_o_val == i
+ assert scl_o_val == i
+ assert sda_oe_val == i
+ assert scl_oe_val == i
+
+ print("I2C Test PASSED!")
+
+# JTAG boundary scan reg addresses - See c4m/nmigen/jtag/tap.py line #357
+BS_EXTEST = 0
+BS_INTEST = 0
+BS_SAMPLE = 2
+BS_PRELOAD = 2
+
+def test_jtag_bs_chain(dut):
+ # print(dir(dut.jtag))
+ # print(dir(dut))
+ # print(dut.jtag._ir_width)
+ # print("JTAG I/O dictionary of core/pad signals:")
+ # print(dut.jtag.ios.keys())
+
+ print("JTAG BS Reset")
+ yield from jtag_set_reset(dut.jtag)
+
+ # TODO: cleanup!
+ # Based on number of ios entries, produce a test shift reg pattern
+ bslen = len(dut.jtag.ios)
+ bsdata = 2**bslen - 1 # Fill with all 1s for now
+ fulldata = bsdata # for testing
+ emptydata = 0 # for testing
+
+ mask_i = produce_ios_mask(dut, is_i=True, is_o=False, is_oe=False)
+ mask_i_oe = produce_ios_mask(dut, is_i=True, is_o=False, is_oe=True)
+ mask_o = produce_ios_mask(dut, is_i=False, is_o=True, is_oe=False)
+ mask_oe = produce_ios_mask(dut, is_i=False, is_o=False, is_oe=True)
+ mask_o_oe = produce_ios_mask(dut, is_i=False, is_o=True, is_oe=True)
+ mask_low = 0
+ mask_all = 2**bslen - 1
+
+ num_bit_format = "{:0" + str(bslen) + "b}"
+ print("Masks (LSB corresponds to bit0 of the BS chain register!)")
+ print("Input only :", num_bit_format.format(mask_i))
+ print("Input and oe:", num_bit_format.format(mask_o_oe))
+ print("Output only :", num_bit_format.format(mask_o))
+ print("Out en only :", num_bit_format.format(mask_oe))
+ print("Output and oe:", num_bit_format.format(mask_o_oe))
+
+ yield from jtag_unit_test(dut, BS_EXTEST, False, bsdata, mask_o_oe, mask_o)
+ yield from jtag_unit_test(dut, BS_SAMPLE, False, bsdata, mask_low, mask_low)
+
+ # Run through GPIO, UART, and I2C tests so that all signals are asserted
+ yield from test_gpios(dut)
+ yield from test_uart(dut)
+ yield from test_i2c(dut)
+
+ bsdata = emptydata
+ yield from jtag_unit_test(dut, BS_EXTEST, True, bsdata, mask_i, mask_i_oe)
+ yield from jtag_unit_test(dut, BS_SAMPLE, True, bsdata, mask_all, mask_all)
+
+ print("JTAG Boundary Scan Chain Test PASSED!")
+
+# ONLY NEEDED FOR DEBUG - MAKE SURE TAP DRIVER FUNCTIONS CORRECT FIRST!
+def swap_bit_order(word, wordlen):
+ rev_word = 0
+ for i in range(wordlen):
+ rev_word += ((word >> i) & 0x1) << (wordlen-1-i)
+
+ num_bit_format = "{:0" + str(wordlen) + "b}"
+ print_str = "Orig:" + num_bit_format + " | Bit Swapped:" + num_bit_format
+ print(print_str.format(word, rev_word))
+
+ return rev_word
+
+def jtag_unit_test(dut, bs_type, is_io_set, bsdata, exp_pads, exp_tdo):
+ bslen = len(dut.jtag.ios) #* 2
+ print("Chain len based on jtag.ios: {}".format(bslen))
+ if bs_type == BS_EXTEST:
+ print("Sending TDI data with core/pads disconnected")
+ elif bs_type == BS_SAMPLE:
+ print("Sending TDI data with core/pads connected")
+ else:
+ raise Exception("Unsupported BS chain mode!")
+
+ if is_io_set:
+ print("All pad inputs/core outputs set, bs data: {0:b}"
+ .format(bsdata))
+ else:
+ print("All pad inputs/core outputs reset, bs data: {0:b}"
+ .format(bsdata))
+
+ result = yield from jtag_read_write_reg(dut.jtag, bs_type, bslen, bsdata)
+ if bs_type == BS_EXTEST:
+ # TDO is only outputting previous BS chain data, must configure to
+ # output BS chain to the main shift register
+
+ # Previous test may not have been EXTEST, need to switch over
+ yield from jtag_set_shift_dr(dut.jtag)
+ result = yield from tms_data_getset(dut.jtag, bs_type, bslen, bsdata)
+ yield from jtag_set_idle(dut.jtag)
+
+ # TODO: make format based on bslen, not a magic number 20-bits wide
+ print("TDI BS Data: {0:020b}, Data Length (bits): {1}"
+ .format(bsdata, bslen))
+ print("TDO BS Data: {0:020b}".format(result))
+ yield from check_ios_keys(dut, result, exp_pads, exp_tdo)
+
+ #yield # testing extra clock
+ # Reset shift register between tests
+ yield from jtag_set_reset(dut.jtag)
+
+def check_ios_keys(dut, tdo_data, test_vector, exp_tdo):
+ print("Checking ios signals with TDO and given test vectors")
+ bslen = len(dut.jtag.ios)
+ ios_keys = list(dut.jtag.ios.keys())
+ print(" ios Signals | From TDO | --- | ----")
+ print("Side|Exp|Seen | Side|Exp|Seen | I/O | Name")
+ for i in range(0, bslen):
+ signal = ios_keys[i]
+ exp_pad_val = (test_vector >> i) & 0b1
+ exp_tdo_val = (exp_tdo >> i) & 0b1
+ tdo_value = (tdo_data >> i) & 0b1
+ # Only observed signals so far are outputs...
+ # TODO: Cleanup!
+ if check_if_signal_output(ios_keys[i]):
+ temp_result = yield dut.jtag.boundary_scan_pads[signal]['o']
+ print("Pad |{0:3b}|{1:4b} | Core|{2:3b}|{3:4b} | o | {4}"
+ .format(exp_pad_val, temp_result, exp_tdo_val, tdo_value, signal))
+ # ...or inputs
+ elif check_if_signal_input(ios_keys[i]):
+ temp_result = yield dut.jtag.boundary_scan_pads[signal]['i']
+ print("Pad |{0:3b}|{1:4b} | Pad |{2:3b}|{3:4b} | i | {4}"
+ .format(exp_pad_val, temp_result, exp_tdo_val, tdo_value, signal))
+ else:
+ raise Exception("Signal in JTAG ios dict: " + signal
+ + " cannot be determined as input or output!")
+ assert temp_result == exp_pad_val
+ assert tdo_value == exp_tdo_val
+
+# TODO: may need to expand to support further signals contained in the
+# JTAG module ios dictionary!
+
+
+def check_if_signal_output(signal_str):
+ if ('__o' in signal_str) or ('__tx' in signal_str):
+ return True
+ else:
+ return False
+
+
+def check_if_signal_input(signal_str):
+ if ('__i' in signal_str) or ('__rx' in signal_str):
+ return True
+ else:
+ return False
+
+
+def produce_ios_mask(dut, is_i=False, is_o=True, is_oe=False):
+ if is_i and not(is_o) and not(is_oe):
+ mask_type = "input"
+ elif not(is_i) and is_o:
+ mask_type = "output"
+ else:
+ mask_type = "i={:b} | o={:b} | oe={:b} ".format(is_i, is_o, is_oe)
+ print("Determine the", mask_type, "mask")
+ bslen = len(dut.jtag.ios)
+ ios_keys = list(dut.jtag.ios.keys())
+ mask = 0
+ for i in range(0, bslen):
+ signal = ios_keys[i]
+ if (('__o' in ios_keys[i]) or ('__tx' in ios_keys[i])):
+ if ('__oe' in ios_keys[i]):
+ if is_oe:
+ mask += (1 << i)
+ else:
+ if is_o:
+ mask += (1 << i)
+ else:
+ if is_i:
+ mask += (1 << i)
+ return mask
+
+
+def print_all_ios_keys(dut):
+ print("Print all ios keys")
+ bslen = len(dut.jtag.ios)
+ ios_keys = list(dut.jtag.ios.keys())
+ for i in range(0, bslen):
+ signal = ios_keys[i]
+ # Check if outputs are asserted
+ if ('__o' in ios_keys[i]) or ('__tx' in ios_keys[i]):
+ print("Pad Output | Name: ", signal)
+ else:
+ print("Pad Input | Name: ", signal)
+
+
+# Copied from test_jtag_tap.py
+# JTAG-ircodes for accessing DMI
+DMI_ADDR = 5
+DMI_READ = 6
+DMI_WRRD = 7
+
+# JTAG-ircodes for accessing Wishbone
+WB_ADDR = 8
+WB_READ = 9
+WB_WRRD = 10
+
+
+def test_jtag_dmi_wb():
+ print(dir(top.jtag))
+ print(dir(top))
+ print("JTAG BS Reset")
+ yield from jtag_set_reset(top.jtag)
+
+ print("JTAG I/O dictionary of core/pad signals:")
+ print(top.jtag.ios.keys())
+
+ # Copied from test_jtag_tap
+ # Don't know if the ID is the same for all JTAG instances
+ ####### JTAGy stuff (IDCODE) ######
+
+ # read idcode
+ idcode = yield from jtag_read_write_reg(top.jtag, 0b1, 32)
+ print("idcode", hex(idcode))
+ assert idcode == 0x18ff
+
+ ####### JTAG to DMI ######
+
+ # write DMI address
+ yield from jtag_read_write_reg(top.jtag, DMI_ADDR, 8, DBGCore.CTRL)
+
+ # read DMI CTRL register
+ status = yield from jtag_read_write_reg(top.jtag, DMI_READ, 64)
+ print("dmi ctrl status", hex(status))
+ #assert status == 4
+
+ # write DMI address
+ yield from jtag_read_write_reg(top.jtag, DMI_ADDR, 8, 0)
+
+ # write DMI CTRL register
+ status = yield from jtag_read_write_reg(top.jtag, DMI_WRRD, 64, 0b101)
+ print("dmi ctrl status", hex(status))
+ # assert status == 4 # returned old value (nice! cool feature!)
+
+ # write DMI address
+ yield from jtag_read_write_reg(top.jtag, DMI_ADDR, 8, DBGCore.CTRL)
+
+ # read DMI CTRL register
+ status = yield from jtag_read_write_reg(top.jtag, DMI_READ, 64)
+ print("dmi ctrl status", hex(status))
+ #assert status == 6
+
+ # write DMI MSR address
+ yield from jtag_read_write_reg(top.jtag, DMI_ADDR, 8, DBGCore.MSR)
+
+ # read DMI MSR register
+ msr = yield from jtag_read_write_reg(top.jtag, DMI_READ, 64)
+ print("dmi msr", hex(msr))
+ #assert msr == 0xdeadbeef
+
+ ####### JTAG to Wishbone ######
+
+ # write Wishbone address
+ yield from jtag_read_write_reg(top.jtag, WB_ADDR, 16, 0x18)
+
+ # write/read wishbone data
+ data = yield from jtag_read_write_reg(top.jtag, WB_WRRD, 16, 0xfeef)
+ print("wb write", hex(data))
+
+ # write Wishbone address
+ yield from jtag_read_write_reg(top.jtag, WB_ADDR, 16, 0x18)
+
+ # write/read wishbone data
+ data = yield from jtag_read_write_reg(top.jtag, WB_READ, 16, 0)
+ print("wb read", hex(data))
+
+ ####### done - tell dmi_sim to stop (otherwise it won't) ########
+
+ top.jtag.stop = True
+
+
+def test_debug_print(dut):
+ print("Test used for getting object methods/information")
+ print("Moved here to clear clutter of gpio test")
+
+ print("printing out info about the resource gpio0")
+ print(dut.gpio['gpio0']['i'])
+ print("this is a PIN resource", type(dut.gpio['gpio0']['i']))
+ # yield can only be done on SIGNALS or RECORDS,
+ # NOT Pins/Resources gpio0_core_in = yield top.gpio['gpio0']['i']
+ #print("Test gpio0 core in: ", gpio0_core_in)
+
+ print("JTAG")
+ print(dut.jtag.__class__.__name__, dir(dut.jtag))
+ print("TOP")
+ print(dut.__class__.__name__, dir(dut))
+ print("PORT")
+ print(dut.ports.__class__.__name__, dir(dut.ports))
+ print("GPIO")
+ print(dut.gpio.__class__.__name__, dir(dut.gpio))
+
+ print("UART")
+ print(dir(dut.jtag.boundary_scan_pads['uart_0__rx__pad__i']))
+ print(dut.jtag.boundary_scan_pads['uart_0__rx__pad__i'].keys())
+ print(dut.jtag.boundary_scan_pads['uart_0__tx__pad__o'])
+ # print(type(dut.jtag.boundary_scan_pads['uart_0__rx__pad__i']['rx']))
+ print("jtag pad table keys")
+ print(dut.jtag.resource_table_pads.keys())
+ print(type(dut.jtag.resource_table_pads[('uart', 0)].rx.i))
+ print(dut.jtag.boundary_scan_pads['uart_0__rx__i'])
+
+ print("I2C")
+ print(dut.jtag.boundary_scan_pads['i2c_0__sda__i'])
+ print(type(dut.jtag.boundary_scan_pads['i2c_0__sda__i']['i']))
+
+ print(dut.jtag.resource_table_pads)
+ print(dut.jtag.boundary_scan_pads)
+
+ # Trying to read input from core side, looks like might be a pin...
+ # XXX don't "look like" - don't guess - *print it out*
+ #print ("don't guess, CHECK", type(top.gpio.gpio0.i))
+
+ print() # extra print to divide the output
+ yield
+
+
+def setup_blinker(build_blinker=False):