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Grammar
[yosys.git]
/
techlibs
/
anlogic
/
drams_map.v
diff --git
a/techlibs/anlogic/drams_map.v
b/techlibs/anlogic/drams_map.v
index 87cbb6a456f27671536855801d511d0b56491e1f..084e2a25feec10492abd47e0b243dbcc2c2da492 100644
(file)
--- a/
techlibs/anlogic/drams_map.v
+++ b/
techlibs/anlogic/drams_map.v
@@
-1,4
+1,5
@@
module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+ parameter [63:0]INIT = 64'bx;
input CLK1;
input [3:0] A1ADDR;
input CLK1;
input [3:0] A1ADDR;
@@
-8,7
+9,9
@@
module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
input [3:0] B1DATA;
input B1EN;
input [3:0] B1DATA;
input B1EN;
- EG_LOGIC_DRAM16X4 _TECHMAP_REPLACE_ (
+ EG_LOGIC_DRAM16X4 #(
+ `include "dram_init_16x4.vh"
+ ) _TECHMAP_REPLACE_ (
.di(B1DATA),
.waddr(B1ADDR),
.wclk(CLK1),
.di(B1DATA),
.waddr(B1ADDR),
.wclk(CLK1),