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efinix: Nuke efinix_gbuf in favor of clkbufmap.
[yosys.git]
/
techlibs
/
efinix
/
cells_sim.v
diff --git
a/techlibs/efinix/cells_sim.v
b/techlibs/efinix/cells_sim.v
index 2fc2034a6508a5bb411285808266274484ba20c0..22c7bc776dafa88d36d2d2801ae9dffbbb5edeee 100644
(file)
--- a/
techlibs/efinix/cells_sim.v
+++ b/
techlibs/efinix/cells_sim.v
@@
-36,6
+36,7
@@
module EFX_FF(
output reg Q,
input D,
input CE,
output reg Q,
input D,
input CE,
+ (* clkbuf_sink *)
input CLK,
input SR
);
input CLK,
input SR
);
@@
-59,7
+60,9
@@
module EFX_FF(
assign ce = CE_POLARITY ? CE : ~CE;
assign sr = SR_POLARITY ? SR : ~SR;
assign d = D_POLARITY ? D : ~D;
assign ce = CE_POLARITY ? CE : ~CE;
assign sr = SR_POLARITY ? SR : ~SR;
assign d = D_POLARITY ? D : ~D;
-
+
+ initial Q = 1'b0;
+
generate
if (SR_SYNC == 1)
begin
generate
if (SR_SYNC == 1)
begin
@@
-98,6
+101,7
@@
endmodule
module EFX_GBUFCE(
input CE,
input I,
module EFX_GBUFCE(
input CE,
input I,
+ (* clkbuf_driver *)
output O
);
parameter CE_POLARITY = 1'b1;
output O
);
parameter CE_POLARITY = 1'b1;
@@
-113,11
+117,13
@@
module EFX_RAM_5K(
input [WRITE_WIDTH-1:0] WDATA,
input [WRITE_ADDR_WIDTH-1:0] WADDR,
input WE,
input [WRITE_WIDTH-1:0] WDATA,
input [WRITE_ADDR_WIDTH-1:0] WADDR,
input WE,
+ (* clkbuf_sink *)
input WCLK,
input WCLKE,
output [READ_WIDTH-1:0] RDATA,
input [READ_ADDR_WIDTH-1:0] RADDR,
input RE,
input WCLK,
input WCLKE,
output [READ_WIDTH-1:0] RDATA,
input [READ_ADDR_WIDTH-1:0] RADDR,
input RE,
+ (* clkbuf_sink *)
input RCLK
);
parameter READ_WIDTH = 20;
input RCLK
);
parameter READ_WIDTH = 20;
@@
-170,4
+176,4
@@
module EFX_RAM_5K(
(WRITE_WIDTH == 10) ? 9 : // 512x10
(WRITE_WIDTH == 5) ? 10 : -1; // 1024x5
(WRITE_WIDTH == 10) ? 9 : // 512x10
(WRITE_WIDTH == 5) ? 10 : -1; // 1024x5
-endmodule
\ No newline at end of file
+endmodule